PCI-DAS6030 & PCI-DAS6032 User's Guide
Functional Details
18
DAQ signal timing
The DAQ timing signals are:
SCANCLK
A/D START TRIGGER
A/D STOP TRIGGER
STARTSCAN
SSH
A/D CONVERT
A/D PACER GATE
A/D EXTERNAL TIME BASE
A/D STOP
ATRIG
SCANCLK signal
SCANCLK is an output signal that may be used for switching external multiplexers. It is a 400 ns wide pulse
that follows the CONVERT signal after a 50 ns delay. This is adequate time for the analog input signal to be
acquired so that the next signal may be switched in. The polarity of the SCANCLK signal is programmable. The
default output pin for the SCANCLK signal is AUXOUT2, but any of the AUXOUT pins may be programmed
as a SCANCLK output.
Figure 5. SCANCLK signal timing
A/D START TRIGGER signal
Use the A/D START TRIGGER signal for conventional triggering (when you only need to acquire data after a
trigger event). Figure 6 shows the A/D START TRIGGER signal timing for a conventionally triggered
acquisition.
Figure 6. Data acquisition example for conventional triggering
The A/D START TRIGGER source is programmable and may be set to any of the AUXIN inputs or to the
DAQ-Sync DS A/D START TRIGGER input. The polarity of this signal is also programmable to trigger
acquisitions on either the positive or negative edge.
The A/D START TRIGGER signal is also available as an output and can be programmed to appear at any of the
AUXOUT outputs. Refer to Figure 7 and Figure 8 for A/D START TRIGGER input and output timing
requirements.
CONVERT
SCANCLK
t
d
t
d
t
w
t
d
= 50 ns
t
w
= 400 ns
A/D Start Trigger
Start Scan
Convert
1
2
3
4
0
Scan Counter
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