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PCI-DAS6030 & PCI-DAS6032 User's Guide 

Functional Details 

23 

 

Figure 18. ATRIG Circuit 

The next section includes a detailed description of each mode of operation. In each case, a ±2V triangle 
waveform is used as the ATRIG input source. The THRESH_HI is set to 1.0V and the THRESH_LO signal is 
set to -1.0V. 

In the following analog trigger signal diagrams, the bold portion of the waveform indicates the data acquired for 
the given ATRIG mode. 

Trigger Above 

The acquisition will begin when the ATRIG signal first goes above the THRESH_HI. This mode is non-
retriggerable. 

 

Figure 19. Trigger Positive Slope 

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Summary of Contents for PCI-DAS6030

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...DAS6030 and PCI DAS6032 Analog and Digital I O User s Guide Document Revision 8A December 2012 Copyright 2012 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg c...

Page 3: ...al by photocopying recording or otherwise without the prior written permission of Measurement Computing Corporation Notice Measurement Computing Corporation does not authorize any Measurement Computin...

Page 4: ...uration 9 Signal connections 10 SCSI connector 10 DAQ Sync connector 14 Field wiring signal termination and conditioning 14 Chapter 3 Functional Details 15 Basic architecture 15 Auxiliary input output...

Page 5: ...y 38 Analog output pacing and triggering 39 Analog trigger 39 Analog I O calibration 40 Digital I O 40 Interrupt Section 41 Counters 41 Configurable AUXIN 5 0 AUXOUT 2 0 external trigger clocks 42 DAQ...

Page 6: ...xt Italic text is used for the names of manuals and help topic titles and to emphasize a word or phrase Where to find more information Additional information about PCI DAS6030 and PCI DAS6032 hardware...

Page 7: ...Six pins are configurable as inputs and three are configurable as outputs Refer to Chapter 3 Functional Details and Chapter 5 Specifications for more information The PCI DAS6030 and PCI DAS6032 provi...

Page 8: ...ceived with the device and includes information about installing the software Please read this booklet completely before installing any software or hardware Optional components If you ordered any of t...

Page 9: ...board into any available PCI slot 2 Close your computer and turn it on If you are using an operating system with support for plug and play a dialog box notifies you that new hardware has been detected...

Page 10: ...together and using that node as the reference input When configured for non referenced single ended input mode 16 analog input channels are available In this mode each input signal is not referenced t...

Page 11: ...le cables C100HD50 x unshielded ribbon cable x 3 or 6 feet Figure 1 C100MMS x shielded round cable x 1 2 or 3 meters Figure 2 Compatible accessory products with the C100HD50 x cable ISO RACK16 P ISO D...

Page 12: ...87 37 D A GND DIO1 86 36 D A OUT 0 DIO0 85 35 AISENSE n c 84 34 n c n c 83 33 n c n c 82 32 n c n c 81 31 n c n c 80 30 n c n c 79 29 n c n c 78 28 n c n c 77 27 n c n c 76 26 n c n c 75 25 n c n c 7...

Page 13: ...3 88 38 D A OUT1 DIO2 87 37 D A GND DIO1 86 36 D A OUT 0 DIO0 85 35 AISENSE n c 84 34 n c n c 83 33 n c n c 82 32 n c n c 81 31 n c n c 80 30 n c n c 79 29 n c n c 78 28 n c n c 77 27 n c n c 76 26 n...

Page 14: ...accessories aspx 1 50 2 49 51 100 52 99 100 50 51 1 Strain relief is stamped Pins 1 50 Pins 1 50 are on the long side of the D connector Pins 51 100 are on the short side of the D connector Key Key Th...

Page 15: ...nd BNC adapters Use with the C100HD50 x cable CIO MINI50 50 pin universal screw terminal accessory CIO TERM100 16x4 screw terminal SCB 50 50 conductor shielded signal connection screw terminal box pro...

Page 16: ...re are three buffer memories provided on the memory bus The queue buffer 8K configuration memory stores programmed channel numbers gains and offsets The ADC buffer 8K FIFO First In First Out temporari...

Page 17: ...Trigger Out Default selections summary AUXIN0 A D CONVERT AUXIN1 A D START TRIGGER AUXIN2 A D STOP TRIGGER AUXIN3 D A UPDATE AUXIN4 D A START TRIGGER AUXIN5 A D PACER GATE AUXOUT0 D A UPDATE AUXOUT1...

Page 18: ...ve one master and up to three slaves SYNC CLK is the 40 MHz time base used to derive all board timing and control The master provides this clock to the slave boards so that all boards in the DAQ sync...

Page 19: ...gnal Use the A D START TRIGGER signal for conventional triggering when you only need to acquire data after a trigger event Figure 6 shows the A D START TRIGGER signal timing for a conventionally trigg...

Page 20: ...ost trigger samples should be acquired It is available as an output and an input By default it is available at AUXIN2 as an input but may be programmed for access at any of the AUXIN pins or the DAQ S...

Page 21: ...tw tw 50 ns Figure 12 STARTSCAN start of scan timing SSH signal The SSH signal can be used as a control signal for external sample hold circuits The SSH signal is a programmable polarity pulse that is...

Page 22: ...on board pacer circuit unless the external clock option is in use This signal may be gated by hardware A D PACER GATE or software A D PACER GATE signal The A D PACER GATE signal is used to disable sc...

Page 23: ...the acquisition based on the gate condition There are two possible inputs for the analog trigger source see Figure 18 The first is the AUXIN0 ATRIG pin on the 100 pin I O connector This is a software...

Page 24: ...I is set to 1 0V and the THRESH_LO signal is set to 1 0V In the following analog trigger signal diagrams the bold portion of the waveform indicates the data acquired for the given ATRIG mode Trigger A...

Page 25: ...te Above Data acquisition is enabled whenever ATRIG goes above the THRESH_HI level Acquisition is suspended whenever the ATRIG signal goes below the THRESH_HI level This is a level sensitive gating mo...

Page 26: ...egative Hysteresis Data acquisition is enabled whenever ATRIG goes above the THRESH_HI level Acquisition is suspended whenever the ATRIG signal goes below the THRESH_LO level The hysteresis level is s...

Page 27: ...e Figure 24 Gate Positive Hysteresis Gate Inside Window Data acquisition is enabled whenever ATRIG is below the THRESH_HI level and above the THRESH_LO level Acquisition is suspended whenever the ATRI...

Page 28: ...XIN pin can be programmed to serve as the D A START TRIGGER signal It is also available as an output on any AUXOUT pin When used as an input the D A START TRIGGER signal may be software selected as ei...

Page 29: ...Figure 29 and Figure 30 show the input and output timing requirements for the D A CONVERT signal Rising Edge Polarity tw tw 37 5 ns minimum Falling Edge Polarity Figure 29 D A CONVERT input signal ti...

Page 30: ...ncy is 10 MHz There is no minimum frequency specified Figure 32 shows the timing requirements for the CTR1 CLK signal Figure 32 CTR1 CLK signal timing CTR1 GATE signal You can use the CTR1 GATE signal...

Page 31: ...e CTR2 CLK pin rather than using the on board 10 MHz or 100 kHz sources It is also polarity programmable The maximum input frequency is 10 MHz There is no minimum frequency specified Figure 35 shows t...

Page 32: ...82C54 chip For detailed information on counter operations please refer to the data sheet on our web site at http www measurementcomputing com PDFmanuals 82C54 pdf Figure 37 shows the timing of the CT...

Page 33: ...ent calibration ensures that your board is operating at optimum calibration values Calibration theory Analog inputs are calibrated for offset and gain Offset calibration for the analog inputs is perfo...

Page 34: ...m DAC is used to adjust the gain of the DAC A separate DAC is used to adjust offset on the final output amplifier The calibration circuits are duplicated for both analog outputs see Figure 39 Figure 3...

Page 35: ...selectable option burst rate 10 S A D gate sources External digital A D GATE External analog ATRIG input CH0 IN through CH15 IN A D gating modes External digital Programmable active high or active lo...

Page 36: ...ents all values are Range of Reading Offset V Noise Quantization V Temp Drift C Absolute Accuracy at FS mV Single Pt Averaged Note 1 10 V 0 0061 479 2 634 1 54 9 0 0001 1 147 5 V 0 0361 243 6 317 1 27...

Page 37: ...a channel to settle to within a specified accuracy in response to a full scale FS step Two channels are scanned at the specified rate A FS DC signal is presented to channel 1 a FS DC signal is present...

Page 38: ...000 W current limiting resistor should be placed in series with each analog input channel being used in applications where the power OFF state sink source current into the board can exceed 20 mA Resis...

Page 39: ...oupling DC Output impedance 0 1 max Power up and reset DACs cleared to 0 volts 20 mV max Table 10 Absolute accuracy specifications Range Absolute Accuracy 10 V 4 7 LSB 0 to 10 V 7 9 LSB Table 11 Absol...

Page 40: ...configurable for Positive or Negative slope DAC pacer out Available at user connector D A PACER OUT RAM buffer size 16 K samples Data transfer DMA Programmed I O Update DACs individually or simultaneo...

Page 41: ...able 16 Digital I O specifications Parameter Specification Digital type Discrete 5V TTL compatible Number of I O 8 Configuration 8 bits independently programmable for input or output All pins pulled u...

Page 42: ...E Interrupt is generated when DAC waveform circuitry is active DAC_DONE Interrupt is generated when a DAC sequence completes DAC_FIFO_1 4_EMPTY Interrupt is generated DAC FIFO is empty DAC_HIGH_CHANNE...

Page 43: ...end of scan A D CONVERT ADC convert pulse SCANCLK Delayed version of ADC convert CTR1 CLK CTR1 clock source D A UPDATE D A update pulse CTR2 CLK CTR2 clock source A D START TRIGGER ADC Start Trigger...

Page 44: ...condensing Mechanical Table 23 Mechanical specifications Parameter Specification Card dimensions L W H PCI half card 174 4 6 87 106 9 4 21 11 65 mm 0 46 in DAQ Sync connector Table 24 DAQ Sync connect...

Page 45: ...e cables C100HD50 x unshielded ribbon cable x 3 or 6 feet C100MMS x shielded round cable x 1 2 or 3 meters Compatible accessory products with C100HD50 x cable ISO RACK16 P ISO DA02 P BNC 16SE BNC 16DI...

Page 46: ...23 n c 73 n c 24 n c 74 n c 25 n c 75 n c 26 n c 76 n c 27 n c 77 n c 28 n c 78 n c 29 n c 79 n c 30 n c 80 n c 31 n c 81 n c 32 n c 82 n c 33 n c 83 n c 34 n c 84 n c 35 AISENSE 85 DIO0 36 D A OUT 0...

Page 47: ...74 n c 25 n c 75 n c 26 n c 76 n c 27 n c 77 n c 28 n c 78 n c 29 n c 79 n c 30 n c 80 n c 31 n c 81 n c 32 n c 82 n c 33 n c 83 n c 34 n c 84 n c 35 AISENSE 85 DIO0 36 D A OUT 0 86 DIO1 37 D A GND 8...

Page 48: ...requency Common Mode Immunity IEC 61000 4 11 2004 Voltage Interrupts To maintain compliance to the standards of this declaration the following conditions must be met The host computer peripheral equip...

Page 49: ...rporation 10 Commerce Way Suite 1008 Norton Massachusetts 02766 508 946 5100 Fax 508 946 9500 E mail info mccdaq com www mccdaq com Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S...

Page 50: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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