PCI-DAS6030 & PCI-DAS6032 User's Guide
Specifications
41
Interrupt Section
Table 17. Interrupt specifications
Parameter
Specification
Interrupts
PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Interrupt enable
Programmable through PLX9080
ADC interrupt sources
(software programmable)
DAQ_ACTIVE: Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:
Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE:
Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE: Interrupt is generated after each conversion completes.
DAQ_EOSCAN: Interrupt is generated after the last channel is converted in multi-
channel scans.
DAQ_EOSEQ: Interrupt is generated after each interval delay during multi-
channel scans.
DAC Interrupt sources
(software programmable)
DAC_ACTIVE: Interrupt is generated when DAC waveform circuitry is active.
DAC_DONE:
Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY:
Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL:
Interrupt is generated when the DAC high channel output is
updated.
Counters
Table 18. Counter specifications
Parameter
Specification
User counter type
82C54
Number of channels
2
Resolution
16-bits
Compatibility
5 V/TTL
CTRn base clock source
(software selectable)
Internal 10 MHz, internal 100 kHz or external connector (CTRn CLK)
Internal 10 MHz clock source
stability
50 ppm
Counter n gate
Available at connector (CTRn GATE)
Counter n output
Available at connector (CTRn OUT)
Clock input frequency
10 MHz max
High pulse width (clock input)
15 ns min
Low pulse width (clock input)
25 ns min
Gate width high
25 ns min
Gate width low
25 ns min
Input low voltage
0.8 V max
Input high voltage
2.0 V min
Output low voltage
0.4 V max
Output high voltage
3.0 V min
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