MaxLinear XR17V358, Manual, Page: 20 / 71

XR17V358
20
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.6
1.4 Device Configuration Registers
The Device Configuration Registers provide easy programming of general operating parameters to the
XR17V358 and for monitoring the status of various functions. These registers control or report on all 8 channel
UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification
and revision, and others.
Table 5 and Table 6 below show these registers in BYTE and DWORD alignment.
Each of these registers is described in detail in the following paragraphs.
T
ABLE
5: D
EVICE
C
ONFIGURATION
R
EGISTERS SHOWN IN
BYTE
ALIGNMENT
A
DDRESS
[A7:A0] R
EGISTER
R
EAD
/W
RITE
C
OMMENT RESET STATE
0x080 INT0 [7:0] Read-only Interrupt [7:0] Bits [7:0] = 0x00
0x081 INT1 [15:8] Read-only Bits [7:0] = 0x00
0x082 INT2 [23:16] Read-only Bits [7:0] = 0x00
0x083 INT3 [31:24] Read-only Bits [7:0] = 0x00
0x084 TIMERCNTL Read/Write Timer Control Bits [7:0] = 0x00
0x085 REGA Reserved Bits [7:0] = 0x00
0x086 TIMERLSB Read/Write Timer LSB Bits [7:0]= 0x00
0x087 TIMERMSB Read/Write Timer MSB Bits [7:0]= 0x00
Individual UART channels can only control the bit
pertaining to that channel in the registers at address
offset 0x088-0x08B.
0x088 8XMODE Read/Write Bits [7:0] = 0x00
0x089 4XMODE Read/Write Bits [7:0] = 0x00
0x08A RESET Write-only Self clear bits after executing Reset Bits [7:0] = 0x00
0x08B SLEEP Read/Write Sleep mode Bits [7:0]= 0x00
0x08C DREV Read-only Device revision Bits [7:0] = Current Rev.
0x08D DVID Read-only Device identification Bits [7:0] = 0x88
0x08E REGB Read/Write EEPROM control Bits [7:0] = 0x00
0x08F MPIOINT[7:0] Read/Write MPIO[7:0] interrupt mask Bits [7:0] = 0x00
0x090 MPIOLVL[7:0] Read/Write MPIO[7:0] level control Bits [7:0] = 0x00
0x091 MPIO3T[7:0] Read/Write MPIO[7:0] output control Bits [7:0] = 0x00
0x092 MPIOINV[7:0] Read/Write MPIO[7:0] input polarity select Bits [7:0] = 0x00
0x093 MPIOSEL[7:0] Read/Write MPIO[7:0] select Bits [7:0] = 0xFF
0x094 MPIOOD[7:0] Read/Write MPIO[7:0] open-drain output control Bits [7:0] = 0x00
0x095 MPIOINT[15:8] Read/Write MPIO[15:8] interrupt mask Bits [15:8] = 0x00
0x096 MPIOLVL[15:8] Read/Write MPIO[15:8] level control Bits [15:8] = 0x00
0x097 MPIO3T[15:8] Read/Write MPIO[15:8] output control Bits [15:8] = 0x00