MaxLinear XR17V358 Manual Download Page 2

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IGURE

2. 176-FPBGA P

INOUT

Transparent Top View

A1 Corner

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Transparent Top View

A1 Corner

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TX5

RI4

GND

CTS4#

TX4

DSR2#

GND

RTS 2#

TMRCK

TEST2

GND

CD5#

DTR5#

CTS5#

CD4 #

DTR4#

RX4

CD2#

DTR2#

RX2

ENIR#

TEST1

GND

VCC33

MPIO0

RI5#

DSR5#

RTS5#

DSR4#

RTS4#

RI2#

CTS 2#

TX2

EN485 #

GND

VCC33

ENABLE

MPIO2

MPIO1

RX5

GND

VCC33

GND

VCC12

GND

VCC33

GND

VCC12

GND

PWRGD

INT

MPIO5

MPIO4

GND

TEST0

RX+

RX-

GND

TX+

TX-

GND

VCC12

CLKREQ#

PERST#

GND

MPIO8

MPIO11

MPIO14

TMS

GND

VCC33

GND

VCC12

GND

CD7#

EEDO

RX0

DSR0#

GND

MPIO9

MPIO12

MPIO15

TRST#

TX3

CTS3#

CD3#

RI3#

DSR6#

TX7

CTS7#

RI7#

TX0

CTS0#

DTR0#

MPIO10

MPIO13

TCK

TDO

RTS3#

DTR3#

RTS 6#

RX6

DTR6#

Ri6#

RX7

DTR7#

EECK

EEDI

RTS0#

RESET#

TDI

GND

RX3

DSR3#

TX6

GND

CTS 6#

CD6#

RTS7#

GND

DSR7#

EECS

CLK

MODE

PRES

GND

DSR1#

CD1#

RX1

CTS1#

RI0#

TX1

MPIO3

VCC12

MPIO6

GND

CLK+

REXT

CLK-

GND

VCC33

VCC12

MPIO7

GND

VCC33

GND

VCC12

SEL

GND

RI1#

VCC33

DTR1#

GND

RTS1#

VCC12

CD0#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TX5

RI4

GND

CTS4#

TX4

DSR2#

GND

RTS 2#

TMRCK

TEST2

GND

CD5#

DTR5#

CTS5#

CD4 #

DTR4#

RX4

CD2#

DTR2#

RX2

ENIR#

TEST1

GND

VCC33

MPIO0

RI5#

DSR5#

RTS5#

DSR4#

RTS4#

RI2#

CTS 2#

TX2

EN485 #

GND

VCC33

ENABLE

MPIO2

MPIO1

RX5

GND

VCC33

GND

VCC12

GND

VCC33

GND

VCC12

GND

PWRGD

INT

MPIO5

MPIO4

GND

TEST0

RX+

RX-

GND

TX+

TX-

GND

VCC12

CLKREQ#

PERST#

GND

MPIO8

MPIO11

MPIO14

TMS

GND

VCC33

GND

VCC12

GND

CD7#

EEDO

RX0

DSR0#

GND

MPIO9

MPIO12

MPIO15

TRST#

TX3

CTS3#

CD3#

RI3#

DSR6#

TX7

CTS7#

RI7#

TX0

CTS0#

DTR0#

MPIO10

MPIO13

TCK

TDO

RTS3#

DTR3#

RTS 6#

RX6

DTR6#

Ri6#

RX7

DTR7#

EECK

EEDI

RTS0#

RESET#

TDI

GND

RX3

DSR3#

TX6

GND

CTS 6#

CD6#

RTS7#

GND

DSR7#

EECS

CLK

MODE

PRES

GND

DSR1#

CD1#

RX1

CTS1#

RI0#

TX1

MPIO3

VCC12

MPIO6

GND

CLK+

REXT

CLK-

GND

VCC33

VCC12

MPIO7

GND

VCC33

GND

VCC12

SEL

GND

RI1#

VCC33

DTR1#

GND

RTS1#

VCC12

CD0#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

ORDERING INFORMATION

(1)

ART

UMBER

PERATING

EMPERATURE

ANGE

EAD

-F

REE

ACKAGE

ACKAGING

ETHOD

XR17V358IB176-F

-40°C to +85°C

Yes

(2)

176-FPBGA

Tray

XR17V358/SP339-0A-EB

XR17V358 8-Channel Evaluation Board

XR17V358/SP339-E4-EB

XR17V358 12-Channel Evaluation Board (Master / Slave)

XR17V358/SP339-E8-EB

XR17V358 16-Channel Evaluation Board (Master / Slave)

OTES

1. Refer to

www.exar.com/XR17V358

for most up-to-date Ordering Information.

2. Visit

www.exar.com

for additional information on Environmental Rating.

XR17V358

HIGH PERFORMANCE OCTAL PCI EXPRESS UART

REV. 1.0.6

Summary of Contents for XR17V358

Page 1: ...S CTS or DTR DSR hardware flow control with programmable hysteresis Automatic Xon Xoff software flow control RS 485 half duplex direction control output with programmable turn around delay Multi drop...

Page 2: ...TMRCK TEST2 GND LX LX NC CD5 DTR5 CTS5 CD4 DTR4 RX4 CD2 DTR2 RX2 ENIR TEST1 GND VCC33 VCC33 VCC33 MPIO0 RI5 DSR5 RTS5 DSR4 RTS4 RI2 CTS2 TX2 EN485 FB GND VCC33 ENABLE D0 MPIO2 MPIO1 RX5 GND VCC33 GND...

Page 3: ...se output active LOW CTS0 N14 I UART channel 0 Clear to Send or general purpose input active LOW If unused a pull up or pull down resistor is recommended on this pin DTR0 N15 O UART channel 0 Data Ter...

Page 4: ...is pin CD2 B7 I UART channel 2 Carrier Detect or general purpose input active LOW If unused a pull up or pull down resistor is recommended on this pin RI2 C7 I UART channel 2 Ring Indicator or general...

Page 5: ...FCTR bit 4 If unused a pull up or pull down resistor is recommended on this pin RTS5 C4 O UART channel 5 Request to Send or general purpose output active LOW CTS5 B3 I UART channel 5 Clear to Send or...

Page 6: ...channel 7 Ring Indicator or general purpose input active LOW If unused a pull up or pull down resistor is recommended on this pin EXPANSION INTERFACE MODE G15 I Expansion Interface Mode Select Connec...

Page 7: ...between master and slave with trace capacitance of less than 25 pF Leave unconnected if no slave device is present PRES H14 I Slave Present has internal pull down resistor In master mode pull this pi...

Page 8: ...ut output 10 This pin defaults to an input with interrupts disabled and is controlled using the MPIOSEL MPIOLVL MPIOINV MPIO3T MPIOOD and MPIOINT configuration registers If unused a pull up or pull do...

Page 9: ...up resistor TDO P4 O JTAG Data Output BUCK REGULATOR SIGNALS ENABLE C14 I Logic 1 enables logic 0 disables buck regulator output LX LX A13 A14 O O Output of internal buck regulator Use 4 7 uH inducto...

Page 10: ...s recommended on this pin VCC33P B13 C13 Pwr 3 3V power supply voltage for output stage of buck regulator VCC33B B14 B15 Pwr 3 3V power supply for the analog blocks of the buck regulator VCC12 D7 D11...

Page 11: ...ing conditions to the cards One of the definitions is the base address loaded into the Base Address Register BAR where the card will be operating in the PCI local bus memory space All this is describe...

Page 12: ...in detail FIGURE 4 THE XR17V358 REGISTER SETS C hannel 0 IN T M PIO TIM E R R EG D evice C onfiguration and U AR T 7 0 C onfiguration R egisters are m apped on to the Base A ddress R egister B AR in a...

Page 13: ...ble 0b 20 RO Capabilities List 1b 19 16 RO Reserved Status bits 0000b 15 11 9 7 5 4 3 2 RO Command bits reserved 0x0000 10 RWR This bit disables the device from asserting INTx logic 1 disable assertio...

Page 14: ...EEPROM by customer 0x0000 0x30 31 0 RO Expansion ROM Base Address Unimplemented 0x00000000 0x34 31 8 RO Reserved returns zeros 0x000000 7 0 RO Capability Pointer 0x50 0x38 31 0 RO Reserved returns ze...

Page 15: ...ot implemented or not applicable return zeros 00b 21 18 RO Not implemented or not applicable return zeros 0000b 17 15 RO L1 Exit Latency 1 us 000b 14 12 RO L0s Exit Latency 64 ns 000b 11 10 RO Active...

Page 16: ...14 Final Address If 1 this will be the last data to be read If 0 there will be more data to be read after this 13 8 Reserved Bits must be 0 7 0 Target Address See Table 3 Table 3 shows the Target Addr...

Page 17: ...space These addresses are offset onto the basic memory address a value loaded into the Memory Base Address Register BAR in the PCI local bus configuration register set The UART Configuration Register...

Page 18: ...Only 256 bytes of RX FIFO data 0x0500 0x05FF UART 1 Write FIFO Write Only 256 bytes of TX FIFO data 0x0600 0x07FF UART 1 Read FIFO with errors Read Only 256 bytes of RX FIFO data LSR 0x0800 0x080F UAR...

Page 19: ...FIFO with errors Read Only 256 bytes of RX FIFO data LSR 0x1800 0x180F UART channel 6 Regs Table 13 Table 14 First 8 regs are 16550 compatible 0x1810 0x187F Reserved 0x1880 0x189A DEVICE CONFIGURATION...

Page 20: ...00 0x085 REGA Reserved Bits 7 0 0x00 0x086 TIMERLSB Read Write Timer LSB Bits 7 0 0x00 0x087 TIMERMSB Read Write Timer MSB Bits 7 0 0x00 Individual UART channels can only control the bit pertaining to...

Page 21: ...RT channel 0 interrupts must first be cleared before any of the global interrupts can be reported in INT1 bits 10 8 GLOBAL INTERRUPT REGISTER DWORD default 0x00 00 00 00 INT3 31 24 INT2 23 16 INT1 15...

Page 22: ...r interrupt and MPIO interrupt are only reported in channel 0 of INT1 bits 10 8 These interrupts are not reported in any other location FIGURE 5 THE GLOBAL INTERRUPT REGISTER INT0 INT1 INT2 AND INT3 C...

Page 23: ...as the clock source for the timer counter The timer can be set to be a single shot for a one time event or re triggerable for a periodic signal An interrupt may be generated when the timer times out...

Page 24: ...up a hardware reset or upon the issue of a Timer Reset command are Timer Interrupt Disabled Re triggerable mode selected Internal 125 MHz clock master or 62 5 MHz clock slave selected as clock source...

Page 25: ...are blocked after the Timer has been started Any write to TIMER MSB LSB registers Issue of any command other than Start Timer Stop Timer and Reset Timer Timer Operation in Re triggerable Mode In the...

Page 26: ...ing the TIMERCNTL register or when a Timer Reset command is issued which brings the Timer back to its default settings The TIMERCNTL will read a value of 0x01 when the Timer interrupt is enabled and t...

Page 27: ...f using the 8XMODE the corresponding bit in this register should be logic 0 Ch 6 Ch 7 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0 4XMODE Register Individual UART Channel 4X Clock Mode Enable Bit 7 Bit 6 Bit 5 Bit 4...

Page 28: ...ep mode automatically after all interrupting conditions have been serviced and cleared It will stay in the sleep mode of operation until it is disabled by resetting the SLEEP register bits 1 4 6 Devic...

Page 29: ...tion for signal sharing The MPIO 0 pin can be programmed to show the Timer output When it is programmed to be the Timer output all the above 5 registers lose control over the MPIO 0 pin For details on...

Page 30: ...hen it can be selected to generate an interrupt MPIOINT bit 0 enables input pin MPIO0 for interrupt and bit 7 enables input pin 7 No interrupt is enable if the pin is selected to be an output The inte...

Page 31: ...ate Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MPIOINV 15 0 default 0x00 The MPIO inputs can be inverted by the MPIOINV register A logic 0 default does not invert the input pin logic A log...

Page 32: ...OD register When the MPIOOD register is a logic 0 default the MPIO is not an open drain output A logic 1 enables the MPIO as an open drain output This register has no effect when the MPIO is an input...

Page 33: ...IT FORMAT The XR17V358 supports 32 bit Read and 32 bit Write transactions anywhere in the mapped memory region except reserved areas In addition to utilize this feature fully the device provides a sep...

Page 34: ...w this clearly READ RX FIFO WITH LSR ERRORS BYTE 3 BYTE 2 BYTE 1 BYTE 0 Read n 0 to n 1 FIFO Data n 1 LSR n 1 FIFO Data n 0 LSR n 0 Read n 2 to n 3 FIFO Data n 3 LSR n 3 FIFO Data n 2 LSR n 2 Etc PCI...

Page 35: ...LE 10 TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT 16C550 COMPATIBLE THR and RHR Address Locations For CH0 to CH7 16C550 Compatible CH0 0x0000 Write THR CH0 0x0000 Read RHR CH1 0x0400 Write THR C...

Page 36: ...gisters DLL DLM and DLD provides the capability for selecting the operating data rate Table 11 shows the divisor for some standard and non standard data rates when using the internal 125 MHz clock at...

Page 37: ...R Bit 7 0 default MCR Bit 7 1 DLL DLM and DLD Registers Prescaler Divide by 1 Prescaler Divide by 4 16X 8X or 4X Sampling Rate Clock to Transmitter and Receiver To Other Channels Fractional Baud Rate...

Page 38: ...00 CB 7 0 01 50000 156 25 156 4 16 00 9C 4 0 57600 135 63 135 10 16 00 87 A 0 01 75000 104 17 104 2 16 00 68 3 0 02 100000 78 125 78 2 16 00 4E 2 0 115200 67 82 67 13 16 00 43 D 0 01 153600 50 86 50 1...

Page 39: ...6 00 65 C 0 02 50000 78 13 78 2 16 00 4E 2 0 57600 67 82 67 13 16 00 43 D 0 01 75000 52 08 52 1 16 00 34 1 0 04 100000 39 06 39 1 16 00 27 1 0 115200 33 91 33 14 16 00 21 F 0 09 153600 25 43 25 6 16 0...

Page 40: ...st be started by asserting RTS DTR output pin MCR bit 0 or bit 1 to logic 1 after it is enabled Figure 11 below explains how it works Two interrupts associated with RTS DTR and CTS DSR flow control ha...

Page 41: ...es and fills UARTA receive FIFO 4 When RXA data fills up to its receive FIFO trigger level UARTA activates its RXA data ready interrupt 5 and continues to receive and put data into its FIFO If interru...

Page 42: ...is signal encoding reduces the on time of the infrared LED hence reduces the power consumption See Figure 12 below Typical max data rate for the infrared encoder with a 3 16 of a bit wide pulse is 115...

Page 43: ...mit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending The TX pin is held at HIGH or...

Page 44: ...FO Control Register Read only Write only LCR 7 0 0 0 1 0 DLD Divisor Fractional Read Write LCR 7 1 0 0 1 1 LCR Line Control Register Read Write 0 1 0 0 MCR Modem Control Register Read Write 0 1 0 1 LS...

Page 45: ...Enable 0 0 INT Source Bit 3 INT Source Bit 2 INT Source Bit 1 INT Source Bit 0 LCR 7 0 Delta Flow Cntl Xoff special char 0 0 1 0 FCR W RXFIFO Trigger RXFIFO Trigger 0 0 DMA Mode TX FIFO Reset RX FIFO...

Page 46: ...by FCR bit 0 A THR empty interrupt can be generated when it is enabled in IER bit 1 3 6 2 Transmitter Operation in non FIFO Mode The host loads transmit data to THR one character at a time The THR emp...

Page 47: ...output is not changed until the last stop bit of the last character is shifted out 3 6 4 Auto RS485 Operation The auto RS485 half duplex direction control changes the behavior of the transmitter when...

Page 48: ...er to prevent false framing If there were any error s they are reported in the LSR register bits 4 1 Upon unloading the receive data byte from RHR the receive FIFO pointer is bumped and the error flag...

Page 49: ...te and enables the receiver if the address matches its slave address otherwise it does not enable the receiver If the receiver has been enabled the receiver will receive the subsequent data If an addr...

Page 50: ...if they have parity errors DLD 4 Fast IR Mode Logic 0 If IR mode is enabled IR pulsewidth will be 3 16th of bit time Logic 1 If IR mode is enabled IR pulsewidth will be 1 4th of bit time 4 4 Interrupt...

Page 51: ...rrupt default Logic 1 Enable the software flow control receive Xoff interrupt See Software Flow Control section for details IER 4 Reserved IER 3 Modem Status Interrupt Enable The Modem Status Register...

Page 52: ...pending interrupt is serviced The Interrupt Source Table Table 15 shows the data values bit 5 0 for the six prioritized interrupt levels and the interrupt sources associated with each of these interru...

Page 53: ...ogic 1 No interrupt pending default condition 4 6 FIFO Control Register FCR Write Only This register is used to enable the FIFOs clear the FIFOs set the transmit receive FIFO trigger levels and select...

Page 54: ...ve Logic 0 No receive FIFO reset default Logic 1 Reset the receive FIFO pointers and FIFO level counter logic the receive shift register is not cleared or altered This bit will return to a logic 0 aft...

Page 55: ...Logic 0 No TX break condition default Logic 1 Forces the transmitter output TX to a space LOW for alerting the remote receiver of a line break condition LCR 5 TX and RX Parity Select If the parity bi...

Page 56: ...nsmitted character The receiver must be programmed to check the same format LCR 3 TX and RX Parity Select Parity or no parity can be selected via this bit The parity bit is a simple way used in commun...

Page 57: ...e Xon Any function In this mode any RX character received will enable Xon resume data transmission MCR 4 Internal Loopback Enable Logic 1 Disable loopback mode default Logic 1 Enable local loopback mo...

Page 58: ...is in the FIFO data This bit clears when there are no more errors in the FIFO LSR 6 Transmitter Empty Flag This bit is the Transmitter Empty indicator This bit is set to a logic 1 whenever both the t...

Page 59: ...tatus Normally this bit is the complement of the RI input In the loopback mode this bit is equivalent to bit 2 in the MCR register The RI input may be used as a general purpose input when the modem in...

Page 60: ...S input has changed state since the last time it was monitored A modem status interrupt will be generated if MSR interrupt is enabled IER bit 3 4 11 Modem Status Register MSR Write Only The upper four...

Page 61: ...sable This bit can be used to disable the transmitter by halting the Transmit Shift Register TSR When this bit is set to a logic 1 the bytes already in the FIFO will not be sent out Also any more data...

Page 62: ...led If there is a pending xon xoff character to be sent while the transmitter is disabled it will be transmitted No additional xon xoff characters will be sent Logic 1 Xon xoff software flow control c...

Page 63: ...terrupt from transmit holding to transmit shift register TSR empty If software flow control is enabled the RTS DTR output will not change if the TX FIFO is empty and the RX FIFO level generates an XON...

Page 64: ...ll function as a general purpose output when hardware flow control is disabled Logic 0 Automatic RTS DTR flow control is disabled default Logic 1 Enable Automatic RTS DTR flow control EFR 5 Special Ch...

Page 65: ...e direction of the half duplex transceiver to the transmit mode when data is being transmitted from the UART on the TX output However the RTS DTR output will remain in the receive direction if the TX...

Page 66: ...register will be reset to 0x00 if at anytime the Software Flow Control is disabled XCHAR 7 4 Reserved XCHAR 3 Transmit Xon Indicator If the last transmitted control character was a Xon character or c...

Page 67: ...W FCR Bits 7 0 0x00 EEDI LOW ISR Bits 7 0 0x01 LCR Bits 7 0 0x00 MCR Bits 7 0 0x00 LSR Bits 7 0 0x60 MSR Bits 3 0 logic 0 Bits 7 4 logic levels of the inputs SPR Bits 7 0 0xFF FCTR Bits 7 0 0x00 EFR B...

Page 68: ...GE VCC33 3 3V 10 SYMBOL PARAMETER MIN TYP MAX UNITS CONDITION NOTES VIL Input Low Voltage 0 3 0 6 V VIH Input High Voltage 2 4 VCC33 V VOL Output Low Voltage 0 4 V IOL 6 mA VOH Output High Voltage 2 4...

Page 69: ...MECHANICAL DIMENSIONS 176 FPBGA Revision A Drawing No POD TOP VIEW BOTTOM VIEW TERMINAL DETAILS SIDE VIEW DETAIL A DETAIL B 00000136 XR17V358 69 REV 1 0 6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART...

Page 70: ...COMMENDED LAND PATTERN AND STENCIL 176 FPBGA Revision A Drawing No POD TYPICAL RECOMMENDED STENCIL TYPICAL RECOMMENDED LAND PATTERN 00000136 XR17V358 70 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV 1 0...

Page 71: ...stered trademarks or trademarks of the respective owners with which they are associated 2015 2018 MaxLinear Inc All rights reserved XR17V358 REV 1 0 6 HIGH PERFORMANCE OCTAL PCI EXPRESS UART Corporate...

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Summary of Contents for XR17V358

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