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Maxim Integrated MAX20335 Manual Download Page 41

I

2

C Register Map

REGISTER  ADDRESS

REGISTER 

NAME

R/W

B7

B6

B5

B4

B3

B2

B1

B0

0x00

ChipId

R

Chip_Id[7:1,0] (Read-Only)

0x01

ChipRev

R

Chip_Rev[7:0] (Read-Only)

0x02

StatusA

R

—

—

JeitaStat[2:0]

ChgStat[2:0]

0x03

StatusB

R

UVLOLDO2

UVLOLDO3

ILim

UsbOVP

UsbOk

ThrmSd

ChgThrmReg

ChgTmo

0x04

StatusC

R

—

SysBatLim

ChgSysLim

ThrmBk1

ThrmBk2

ThrmLDO1

ThrmLDO2

ThrmLDO3

0x05

IntA

COR

ThermStatInt

ChgStatInt

ILimInt

UsbOVPInt

UsbOkInt

ChgThrm

 

SdInt

ChgThrm

 

RegInt

ChgTmoInt

0x06

IntB

COR

—

SysBatLimInt

ChgSys

 

LimInt

ThrmBk1Int

ThrmBk2Int

ThrmLDO1Int

ThrmLDO2Int

ThrmLDO3Int

0x07

IntMaskA

R/W

Therm

 

StatIntM

ChgStatIntM

ILimIntM

UsbOVPIntM

UsbOkIntM

ChgThrm

 

SdIntM

ChgThrm

 

RegIntM

ChgTmoIntM

0x08

IntMaskB

R/W

—

SysBatLim

 

IntM

ChgSysLim

 

IntM

ThrmBk1IntM

Thrm

 

Bk2IntM

Thrm

 

LDO1IntM

Thrm

 

LDO2IntM

Thrm

 

LDO3IntM

0x09*

ILimCntl

R/W**

SysMin[2:0]

SysMin[2:0]

SysMin[2:0]

—

—

—

ILimCntl[1:0]

0x0A*

ChgCntlA

R/W**

—

BatReChg[1:0]

BatReg[3:0]

ChgEn

0x0B*

ChgCntlB

R/W**

—

VPChg[2:0]

IPChg[1:0]

ChgDone[1:0]

0x0C*

ChTmr

R/W**

ChgAutoStp

ChgAutoReSta

MtChgTmr[1:0]

FChgTmr[1:0]

PChgTmr[1:0]

0x0D

Buck1Cfg

R/W

Buck1Seq[2:0]

Buck1En[1:0]

Buck1PFWDis

Reserved

0x0E

Buck1VSet

R/W**

Buck1LowEMI

—

Buck1VSet[5:0]

0x0F

Buck2Cfg

R/W

Buck2Seq[2:0]

Buck2En[1:0]

Buck2PFWDis

Reserved

0x10

Buck2VSet

R/W**

Buck2LowEMI

—

Buck2VSet[5:0]

0x1

1

Buck1/2ISet

R/W

Buck2ISet[3:0]

Buck1ISet[3:0]

0x12

LDO1Cfg

R/W

LDO1Seq[2:0]

—

LDO1

 

ActDSC

LDO1En[1:0]

LDO1Mode

MAX20335

PMIC with Ultra-Low I

Q

 Voltage Regulators and 

Battery Chargers for Small Lithium Ion Systems

www.maximintegrated.com

Maxim Integrated  

│

 

41

Summary of Contents for MAX20335

Page 1: ...h the default preconfigured The linear regulators can also be configured to operate as power switches that may be used to disconnect the quiescent load of the system peripherals The MAX20335 features...

Page 2: ...on 25 Block Diagram 27 Detailed Description 27 Power Regulation 27 Power On Off and Reset Control 27 Power Sequencing 30 Smart Power Selector 31 Thermal Current Regulation 31 System Load Switch 32 Inp...

Page 3: ...ev Register 0x01 43 Table 6 StatusA Register 0x02 43 Table 7 StatusB Register 0x03 44 Figure 1 Power Function Input Control Modes Flow Diagrams 29 Figure 2a Power On Sequencing 30 Figure 2b Power On S...

Page 4: ...Table 19 Buck2Cfg Register 0x0F 53 Table 20 Buck2VSet Register 0x10 54 Table 21 Buck1 2ISet Register 0x11 54 Table 22 LDO1Cfg Register 0x12 55 Table 23 LDO1VSet Register 0x13 55 Table 24 LDO2Cfg Regis...

Page 5: ...H SMART POWER SELECTOR BAT THM CAP SYS CHGIN SET MUX DIVIDER SCL SDA INT MPC0 CONTROL GND MAX20335 VSYS VIO L3OUT L3IN MPC1 BUCK 2 B2LX BUCK 1 B1OUT B1LX LDO SWITCH 1 L1IN L1OUT L2IN 1 F 1 F 1 F 10 F...

Page 6: ...IQ Voltage Regulators and Battery Chargers for Small Lithium Ion Systems www maximintegrated com Maxim Integrated 6 Package thermal resistances were obtained using the method described in JEDEC speci...

Page 7: ...IB_OUT 0A IL_OUT 0A 5 2 BUCK REGULATOR 1 VSYS 3 7V L 2 2 H C 2 2 F VB1OUT 1 2V Input Voltage VIN_BUCK1 Input voltage VSYS 2 7 5 5 V Output Voltage VOUT_BUCK1 25mV step resolution 0 7 2 275 V Output UV...

Page 8: ...UCK1 VSYS 3 7V VB1OUT 1 2V 7 3 13 Minimum TON TON_MIN 40 80 ns Maximum Duty Cycle DMAX_BUCK1 Buck1IAdptEnb 0 98 Switching Frequency fSW_BUCK1 Load regulation error 3 3 MHz Average Current During Short...

Page 9: ...3 4V 2 5 2 5 Peak to Peak Ripple VPPRIPPLE2 Buck2ISet 100mA COUT 2 2 F IB2OUT 1mA 10 mV IPEAK Set Range IPEAK_BUCK2 25mA step resolution set by Buck2ISet 3 0 50 375 mA Load Regulation Error VLOADR_BU...

Page 10: ...ctor BOURNS SRP2010 2R2M VB2OUT 1 2V 87 BLX Rising Falling Slew Rate SRBLX_BUCK2 Buck2LowEMI 0 2 V ns Buck2LowEMI 1 0 5 Thermal Shutdown Temperature TSHDN_BUCK2 140 C Thermal Shutdown Temperature Hyst...

Page 11: ...LDO1 VL1IN 3 7V 7 20 37 mA Switch Mode Resistance RON_LDO1 VL1IN 2 7V IL1OUT 100mA 0 5 0 85 VL1IN 1 8V IL1OUT 100mA 0 76 1 3 VL1IN 1 2V IL1OUT 5mA 1 7 2 8 Turn On Time tON_LDO1 IL1OUT 0mA time from 10...

Page 12: ...Voltage VDROP_LDO2 VL2IN 3V IL2OUT_ 100mA LDO2VSet 3V 100 mV Line Regulation Error VLINEREG_LDO2 VL2IN VL2OUT 0 5V to 5 5V 0 4 0 05 0 4 V Load Regulation Error VLOADREG_LDO2 IL2OUT 100 A to 100mA 0 00...

Page 13: ...1 4 1 64 LDO3 C 1 F unless otherwise noted Typical values are at VL3IN 3 7V with IL3OUT 10mA VL3OUT 3V Input Voltage VINLDO3 LDO mode 1 71 5 5 V Switch mode 1 2 5 5 V Quiescent Supply Current IQ_LDO3...

Page 14: ...L3OUT 100mA 0 46 0 76 VL3IN 1 8V IL3OUT 100mA 0 7 1 15 VL3IN 1 2V IL3OUT 5mA 1 7 2 6 Turn On Time tON_LDO3 IL3OUT 0mA time from 10 to 90 of final value 1 5 3 7 ms IL3OUT 0mA time from 10 to 90 of fina...

Page 15: ...t Hysteresis VCHGIN SYS_TP_HYS 275 mV Input Limiter Current ILIM ILimCntl 1 0 00 0 mA ILimCntl 1 0 01 90 100 ILimCntl 1 0 10 450 550 ILimCntl 1 0 11 1000 Internal CAP Regulator VCAP VCHGIN 5V 3 9 4 2...

Page 16: ...switch opens and BAT is connected to SYS through a diode 1 9 2 05 2 2 V BAT UVLO Threshold Hysteresis VBAT_UVLO_HYS Hysteresis 50 mV BATTERY CHARGER See Figure 5a and Figure 5b VBAT 4 2V Typical value...

Page 17: ...n 101 VBAT 3 4V 4 1 SysMin 110 VBAT 3 4V 4 2 SysMin 111 VBAT 3 4V 4 3 Charger Current Soft Start Time tCHG_SOFT 1 ms PRECHARGE Precharge Current IPCHG IPChg 00 5 IFChg IPChg 01 9 10 11 IPChg 10 20 IPC...

Page 18: ...hgDone 00 5 IFChg ChgDone 01 8 5 10 11 5 ChgDone 10 20 ChgDone 11 30 BAT Regulation Voltage Note 7 VBatReg BatReg 0000 4 05 V BatReg 0001 4 10 BatReg 0010 4 15 BatReg 0011 TA 25 C 4 179 4 2 4 221 TA 0...

Page 19: ...e current below which timer clock operates at half speed 50 IFChg Timer Suspend Threshold TIMSUS_THRES If charge current is reduced due to ILIM or TDIE this is the percentage of charge current below w...

Page 20: ...igh SDA SCL MPC0 MPC1 PFN1 PFN2 VIH 1 4 V Input Logic Low SDA SCL MPC0 MPC1 PFN1 PFN2 VIL 0 5 V Output Logic Low SDA RST INT LED PFN2 VOL IOL 4mA 0 4 V High Level Leakage Current SDA RST INT LED PFN2...

Page 21: ...rge current accuracy tested only at 50mA and 500mA all other values guaranteed by design Note 7 Values over temperature are not production tested and guaranteed by characterization Note 8 fSCL must me...

Page 22: ...N LDO1 ON BUCKS ON BUCKS ON ALL LDOS ON 0 1 2 3 4 5 6 0 40 80 120 160 200 0 40 80 120 160 200 240 280 V BAT V I BAT mA TIME minutes IBAT VBAT vs TIME toc05 VBAT IBAT 150mAhr BATTERY IChgDone 1 0 01 IP...

Page 23: ...2OUT 3 0V 0 10 20 30 40 50 60 70 80 90 100 0 001 0 1 10 1000 EFFICIENCY IB2OUT mA BUCK2 EFFICIENCY vs LOAD toc17 VBAT 3 3V VBAT 3 7V VBAT 4 2V VB2OUT 1 8V INDUCTOR TOKO DFE201610E0 2R2M 50mA div toc12...

Page 24: ...100 200 300 400 V B1OUT V IB1OUT mA VB1OUT vs LOAD VB1OUT 1 2V toc23 VBAT 3 3V 3 7V 4 2V 0 10 20 30 40 50 60 70 80 90 100 0 001 0 1 10 1000 EFFICIENCY IB1OUT mA BUCK1 EFFICIENCY vs LOAD toc21 VBAT 3...

Page 25: ...IN LDO2 Input B3 INT Open Drain Active Low Interrupt Output B4 MON Voltage Monitor Pin B5 B6 BAT Battery Connection Connect BAT to a positive battery terminal bypass BAT with a minimum 1 F capacitor t...

Page 26: ...rnal pFET from BAT to SYS Output is pulled to GND when charger is disconnected and internal BAT SYS FET is switched on Otherwise this output is pulled high to the SYS voltage E1 RST Power On Reset Out...

Page 27: ...ases Table 1 describes the behavior of the PFN1 and PFN2 pins based on the PwrRstCfg 3 0 bits and Figure 1 shows basic flow diagrams associated with each mode A Soft Reset generates a 10ms logic low p...

Page 28: ...a CHGIN insertion generates a hard reset after a 200ms delay When PFN2 is high a CHGIN insertion generates a soft reset after a 200ms delay In this mode the device can only enter the off state by wri...

Page 29: ...gure 1 Power Function Input Control Modes Flow Diagrams MAX20335 PMIC with Ultra Low IQ Voltage Regulators and Battery Chargers for Small Lithium Ion Systems www maximintegrated com Maxim Integrated 2...

Page 30: ...the ChgAlwTry setting If ChgAlwTry 0 and an undervoltage condition is detected on SYS during the sequencing process the device turns SYS and all other external resources off and waits for CHGIN remova...

Page 31: ...MAX20335 will attempt to limit the temperature increase by reducing the input current from CHGIN In this condi tion the system load has priority over charger current so the input current is first red...

Page 32: ...d between BAT and SYS remains present when the device is in off mode Input Limiter The input limiter distributes power from the external adapter to the system load and battery charger In addition to t...

Page 33: ...alue of 1V The range of acceptable resistors for RSET is 4k to 400k Thermistor Monitoring with Charger Shutdown The MAX20335 features three modes for controlling charger behavior based on battery pack...

Page 34: ...ARGE CONSTANT CURRENT VBAT_PCHG VBAT VBAT_REG IFCHG_T2 T3 T1 T4 TEMPERATURE C CHARGING NO CHARGING T2 T3 VBATREG REGULATED VOLTAGE RTHM RPA RPU CAP NO CHARGING T1 T4 TEMPERATURE C CHARGING NO CHARGING...

Page 35: ...F As per I2C settings 01 Thermistor Monitoring ON OFF IPCHG IPChg IFChg T1T2IFchg Regulated Voltage VBATREG IPCHG IPChg IFChg T2T3IFchg Regulated Voltage VBATREG OFF OFF 10 JEITA Monitoring 1 ON OFF I...

Page 36: ...CHG 0 FAST CHARGE CV SUSPEND ChgStat 001 LED 1 5s PERIOD ICHG 0 ChgEn 1 VSYS VSYS_LIM RISE VBAT VBAT_PChg RESET CHARGE TIMER VBAT VBAT_PChg RESET CHARGE TIMER VOLTAGE MODE 1 AND VSYS VSYS_LIM RISE VOL...

Page 37: ...T_PChg RESET CHARGE TIMER VBAT VBAT_PChg RESET CHARGE TIMER VOLTAGE MODE 1 AND VSYS VSYS_LIM RISE VOLTAGE MODE 0 AND VSYS VSYS_LIM RISE OR VBAT VBAT_PChg RECOVER FROM FAULT RESET CHARGE TIMER T1 T T4...

Page 38: ...CL clock pulse Changes in SDA while SCL is high and stable are considered control signals see the Start Stop And Repeated Start Conditions section Both SDA and SCL remain high when the bus is not acti...

Page 39: ...ad operation 1 The master sends a START condition 2 The master sends the 7 bit slave address plus a write bit low 3 The addressed slave asserts an ACK on the data line 4 The master sends the 8 bit reg...

Page 40: ...the data line 14 The master generates a STOP condition Acknowledge Bits Data transfers are acknowledged with an acknowledge bit ACK or a not acknowledge bit NACK Both the master and the MAX20335 gene...

Page 41: ...m RegIntM ChgTmoIntM 0x08 IntMaskB R W SysBatLim IntM ChgSysLim IntM ThrmBk1IntM Thrm Bk2IntM Thrm LDO1IntM Thrm LDO2IntM Thrm LDO3IntM 0x09 ILimCntl R W SysMin 2 0 SysMin 2 0 SysMin 2 0 ILimCntl 1 0...

Page 42: ...W LDO2VSet 4 0 0x16 LDO3Cfg R W LDO3Seq 2 0 LDO3 ActDSC LDO3En 1 0 LDO3Mode 0x17 LDO3VSet R W LDO3VSet 4 0 0x18 ThrmCfg R W T1T2IFchg 2 0 T2T3IFchg 2 0 ThermEn 1 0 0x19 ThrmCfg R W T3T4IFchg 2 0 0x1A...

Page 43: ...T1 001 T1 T T2 010 T2 T T3 011 T3 T T4 100 T T4 101 No thermistor detected THM high due to external pullup Note that if a parallel resistor is used for thermistor monitoring this mode may not functio...

Page 44: ...not present or outside of valid range 1 CHGIN Input is present and valid ChgThrmSd Status of Thermal Shutdown 0 Charger and input current limiter is in normal operating mode 1 Charger and input curre...

Page 45: ...t indicates if the input current limit is being actively reduced to maintain a 40mV drop between CHGIN SYS This adaptive input current limit prevents adapter collapse in the case that a power adapter...

Page 46: ...mRegInt Change in ChgThrmReg caused interrupt ChgTmoInt Change in ChgTmo caused interrupt ADDRESS 0x06 MODE Clear On Read BIT 7 6 5 4 3 2 1 0 NAME SysBLimInt VLimInt Thrm Buck1Int Thrm Buck2Int Thrm L...

Page 47: ...6 0 Mask 1 Not masked UsbOVPIntM UsbOVPIntM masks the UsbOVPInt interrupt in the IntA register 0x05 0 Mask 1 Not masked UsbOkM UsbOkM masks the UsbOk interrupt in the IntB register 0x06 0 Mask 1 Not m...

Page 48: ...0 Mask 1 Not masked ThrmLDO1 IntM 0 Mask 1 Not masked ThrmLDO2 IntM 0 Mask 1 Not masked ThrmLDO3 IntM 0 Mask 1 Not masked ADDRESS 0x09 MODE Read Write or Read Only if Write Protect Enabled see Table 3...

Page 49: ...0mV 01 BatReg 120mV 10 BatReg 170mV 11 BatReg 220mV BatReg 3 0 Setting the Battery Regulation Threshold 0000 4 05V 0001 4 10V 0010 4 15V 0011 4 20V 0100 4 25V 0101 4 30V 0110 4 35V 0111 4 4V 1000 4 45...

Page 50: ...oltage threshold setting 000 2 10V 001 2 25V 010 2 40V 111 2 55V 100 2 70V 101 2 85V 110 3 00V 111 3 15V IPChg 1 0 Pre charge current setting 00 0 05 x IFChg 01 0 1 x IFCHG 10 0 2 x IFChg 11 0 3 x IFC...

Page 51: ...a Charger Auto Restart Control 0 Charger remains in maintain charge done even when VBAT is less than charge restart threshold see Charger state diagram 1 Charger automatically restarts when VBAT drops...

Page 52: ...Control Buck1En 1 0 Buck1 Enable Configuration effective only when Buck1Seq 111 00 Disabled Buck1 OUT not actively discharged unless in Hard Reset ShutDown Off Mode 01 Enabled 10 Enabled when MPC0 is...

Page 53: ...n Read only 000 Disabled 001 Reserved 010 Enabled at 0 of Boot POR Process Delay Control 011 Enabled at 25 of Boot POR Process Delay Control 100 Enabled at 50 of Boot POR Process Delay Control 101 Res...

Page 54: ...g falling slopes on BLX by a factor of three Buck2VSet 5 0 Buck2 Output Voltage Setting Linear Scale from 0 7V to 3 85V in 50mV increments 000000 0 7V 000001 0 75V 111111 3 85V ADDRESS 0x11 MODE Read...

Page 55: ...continue to draw additional quiescent current as long at this bit is set to 1 even when the LDO is disabled See EC table LDO1En 1 0 LDO1 Enable Configuration effective only when LDO1Seq 111 00 Disabl...

Page 56: ...aw additional quiescent current as long at this bit is set to 1 even when the LDO is disabled See Electrical Characteristics table LDO2En 1 0 LDO2 Enable Configuration effective only when LDO2Seq 111...

Page 57: ...uiescent current as long at this bit is set to 1 even when the LDO is disabled See EC table LDO3En 1 0 LDO3 Enable Configuration effective only when LDO3Seq 111 00 Disabled LDO s OUT not actively disc...

Page 58: ...g 110 0 8 x IFChg 111 1 x IFChg T2T3IFchg 2 0 Fast Charge Current for T2 T3 Temperature Zone 000 0 2 x IFChg 001 0 3 x IFChg 010 0 4 x IFChg 011 0 5 x IFChg 100 0 6 x IFChg 101 0 7 x IFChg 110 0 8 x I...

Page 59: ...3 1 10 2 1 11 1 1 MONHiZ MON OFF MODE condition 0 Pulled LOW by 100k pull down resistor 1 Hi Z MONCtr 2 0 MON Pin Source selection 40 s BBM after any change of MONCtr 000 MON is not connected to any i...

Page 60: ...try If SYS UVLO condition occurs during boot process 0 Part latches off until CHGIN is removed and replaced 1 Part retries after delay ADDRESS 0x1C MODE Read Only BIT 7 6 5 4 3 2 1 0 NAME ILim_T 2 0 P...

Page 61: ...ciency for loads 100mA 0 FET Scaling disabled 1 FET Scaling enabled Buck1IAdptEnb Buck 1 Peak Current 0 Enable adaptive peak current 1 Peak current set by Buck1ISet 3 0 Buck1Fst Buck1 Fast Start 0 Nor...

Page 62: ...as no effect after being set 0 Shut down 5s after power on 1 Stay on ADDRESS 0x1F MODE Read Write BIT 7 6 5 4 3 2 1 0 NAME PWR_CMD 7 0 PWR_CMD 7 0 Power Command Register Writing the following values i...

Page 63: ...duces switching noise in the IC The impedance of the input capacitors at the switching frequency should be kept very low Ceramic capacitors are recommended due to their small size and low ESR Make sur...

Page 64: ...Disabled Disabled Enabled Disabled Disabled LDO3En 1 0 Enabled Disabled LDO3Seq 2 0 LDO3En LDO3En LDO3En LDO3En LDO3En LDO3Seq 2 0 50 Boot LDO3En VPchg 2 0 3 00V 2 85V 3 00V 3 00V 3 00V VPchg 2 0 3 00...

Page 65: ...0x16 LDO3Cfg 0x82 0xE0 0x17 LDO3VSet 0x00 0x1A 0x04 0x15 0x09 0x17 LDO3VSet 0x09 0x18 0x18 THRMCFA 0xFD 0xFE 0x7E 0x1E 0xFE 0x18 THRMCFA 0x1F 0x7C 0x19 THRMCFB 0x07 0x07 0x07 0x00 0x07 0x19 THRMCFB 0...

Page 66: ...to 85 C 36 WLP MAX20335DEWX T 40 C to 85 C 36 WLP MAX20335FEWX 40 C to 85 C 36 WLP MAX20335FEWX T 40 C to 85 C 36 WLP MAX20335GEWX 40 C to 85 C 36 WLP MAX20335GEWX T 40 C to 85 C 36 WLP MAX20335JEWX 4...

Page 67: ...d added MAX20335JEWX and MAX20335JEWX T to the Ordering Information table 64 66 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim...

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