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Magtrol Model 6510
e
Single-Phase Power Analyzer
Chapter 4 – Operating Principles
THEOR
Y
THEOR
Y
4.2.2.2
Main Program
The main program reads that a sample is ready.
Divide the V register by 256.
Store V in a 24-bit register.
The result is appended to a 32 word circular buffer.
Add buffer contents and divide by 32.
The result is appended to a 2cd 32 word circular buffer.
Divide the I register by 256.
Store I in a 24-bit register.
The result is appended to a 32 word circular buffer.
Add buffer contents and divide by 32.
The result is appended to a 2cd 32 word circular buffer.
Divide the VI register by 256.
Store VI in a 24-bit register.
The result is appended to a 32 word circular buffer.
Add buffer contents and divide by 32.
The result is appended to a 2cd 32 word circular buffer.
Add 2cd V2 buffer contents and divide by 32. Save this value.
Add 2cd I2 buffer contents and divide by 32. Save this value.
Add 2cd VI buffer contents and divide by 32. Save this value.
Each sample is now 256 x (32 + 32) (16384) a/d samples. At
223721.5625 samples per second that is 73.23388 ms for a new input
too fully average.
The VI sample is applied to an RC filter algorithm.
The output of the filter is multiplied by a gain value.
This value is stored for output.
The V sample is applied to an RC filter algorithm.
The output of the filter is multiplied by a gain value.
This value is stored for output.
The I sample is applied to an RC filter algorithm.
The output of the filter is multiplied by a gain value.
This value is stored for output.
These values are updated at 873.912 readings per second.
Every 8th time through the loop or at a rate of 109.239 the V and I
peak values are stored for output and the data ready flag is set.
