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3.6.7 PCI Dynamic Bursting (Enabled)
When Enabled, data transfers on the PCI bus, where possible, make use of
the high-performance PCI bust protocol, in which greater amounts of data
3.6.8 PCI Master 0 WS Write (Enabled)
When Enabled, writes to the PCI bus are command with zero wait states.
3.6.9 PCI Delay Transaction (Enabled)
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
3.6.10 PCI Master Read Prefetch (Enabled)
This item allows you enable/disable the PCI Master Read Prefetch.
3.6.11 PCI #2 Access #1 Retry (Disabled)
This item allows you enable/disable the PCI #2 Access #1 Retry.
3.6.12 AGP Master 1 WS Write (Enabled)
This implements a single delay when writing to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
3.6.13 AGP Master 1 WS Read (Disabled)
This implements a single delay when reading to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
3.6.14 PCI IRQ Actived By (Level)
This sets the method by which the PCI bus recognizes that an IRQ service
is being requested by a device. Under all circumstances, you should retain
the default configuration unless advised otherwise by your system’s
manufacturer.
