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DRAM timing
If the DRAM Timing by SPD item is set to Enabled, the three items below will
automatically be set be the BIOS. To do this the BIOS will read information out of the SPD
EPROM that is located on the DIMM module, this information will tell the BIOS how to
best access the memory. If you set this item to disabled, you can set the memory access
items yourself. A word of warning though, if you are not familiar with DRAM settings do
NOT make any changes (for the sake of system stability). Refer to the table below for the
meaning of the individual DRAM items:
Values
Meaning
100 MHz
If your DIMM modules are PC-100 compliant, select this
setting.
DRAM Clock
133 MHz
Only when your DIMM modules are PC-133 compliant can you
use this setting. In case of instability always select 100MHz.
2
2 is the fastest setting, use this setting only if your DIMM
modules support CAS 2
DRAM Cycle
Length
3
This is the default setting, always use this setting when the
system is unstable.
Disabled
This is the safest setting (default).
2bank
This setting is faster than disabled.
Bank
Interleave
4 bank
This is fastest setting.
Memory Hole
Some old devices need a memory hole to be present between 15M and 16M. CPU Cycles
matching the hole will be passed on to the PCI bus instead of accessing the memory.
Normally you can disable this setting, but if one of your devices needs it set it to enabled.
Values
Meaning
Disabled
There is no memory hole.
Memory Hole
15M – 16M A memory hole exists between 15 and 16MB.
