Chapter 5 Terminal Operation IP6704A TDMoEthernet
Loop Telecommunication International, Inc.
85
IP67 04 A == = Clo ck S our ce D ispl ay = == 13 :49 :46 01/ 18/ 201 6
Mast er_ Clk So urc e : IN TER NAL
Seco nd_ Clk So urc e : IN TER NAL
Curr ent Cl ock : MA STE R_C LK
Clk_ Rec ove r_M ode : AU TOM ATI C
Cloc k S tat us : NO RMA L
Por t B ID Ena ble St atu s
ACR1 : A 0 OFF id le
ACR2 : A 0 OFF id le
ACR3 : A 0 OFF id le
ACR4 : A 0 OFF id le
<< E SC key to re tur n t o p rev iou s m enu , S PAC E ba r t o r efr esh >>
NOTES:
Port A, B, C, D can use BID 0-15
(
Related to table “TimeSlot to Bundle Setup”)
And we can select Port A, B, C, D ACR to BID from 0-15
For example, if we setup Port A E1 Master_Clk Source to ACR1 and ACR1
have two bundles with BID=0&1, and we want to do adaptive clock recovery
from BID=1
Then we can setup as below:
Master_Clk Source : ACR1
Port
BID
Enable
Status
ACR1
A
1
ON
idle
5.12.2.
SyncE Clock Display
The full menu path for Clock Source Display is as follows:
O
> Logon
B
> Clock Source Display
B
> SyncE Clock Display
The screen of SyncE Clock Display will show as below.
Input the port number (A~D): A
IP6704A T1 === SyncE Clock Display === 16:43:50 01/22/2016
Master_Clk Source : A(LINE)
Second_Clk Source : A(LINE)
Current Clock : MASTER_CLK
Clk_Recover_Mode : AUTOMATIC
Clock Status : NORMAL
<< ESC key to return to previous menu, SPACE bar to refresh >>