26
LTC1736
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 10. LTC1736 Layout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
C
OSC
RUN/SS
I
TH
FCB
SGND
PGOOD
SENSE
–
SENSE
+
V
FB
V
OSENSE
VID0
VID1
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
VIDV
CC
VID4
VID3
VID2
LTC1736
1000pF
47pF
C
C1
C
OSC
C
C2
C
SS
R
C
+
4.7
µ
F
L1
EXTERNAL EXTV
CC
CONNECTION
D
B
C
IN
–
–
+
+
C
B
D1
M1
M2
+
R
SENSE
C
OUT
+
V
IN
V
OUT
1736 F10
SENSE
+
SENSE
–
HIGH CURRENT PATH
1736 F11
CURRENT SENSE
RESISTOR
(R
SENSE
)
Figure 11. Kelvin Sensing R
SENSE
2. Does the V
OSENSE
pin connect as close as possible to
the load? The optional 50pF to 100pF capacitor from
V
FB
to SGND should be as close as possible to the
LTC1736.
3. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE
+
and SENSE
–
should be as close as
possible to the LTC1736. Ensure accurate current sens-
ing with kelvin connections as shown in Figure 11.
Series resistance can be added to the SENSE lines to
increase noise rejection.
4. Does the (+) terminal of C
IN
connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci-
tor provides the AC current to the MOSFET(s).
5. Is the INTV
CC
decoupling capacitor connected closely
between
INTV
CC
and the power ground pin? This ca-
pacitor carries the MOSFET driver peak currents. An
additional 1
µ
F ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve
noise performance.
6. Keep the switching node (SW), Top Gate node (TG) and
Boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” (Pins 13 to 24) of the LTC1736 and
occupy minimum PC trace area.
