23
LTC1736
accuracy is
±
1%, so the output transient voltage cannot
exceed
±
0.097V. At V
OUT
= 1.5V, the maximum output
voltage change controlled by the I
TH
pin would be:
∆
=
=
±
= ±
V
Input Offset V
V
V
V
mV
OSENSE
OUT
REF
•
.
• .
.
0 03
1 5
0 8
56
With optimum resistor values at the I
TH
pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional 56mV to the allowable transient
voltage on the output capacitors, a 58% improvement
over the 97mV allowed without active voltage positioning.
The next step is to calculate the I
TH
pin voltage, V
ITH
, scale
factor. The V
ITH
scale factor reflects the I
TH
pin voltage
required for a given load current. V
ITH
controls the peak
sense resistor voltage, which represents the DC output
current plus one half of the peak-to-peak inductor current.
The no load to full load V
ITH
range is from 0.3V to 2.4V,
which controls the sense resistor voltage from 0V to the
∆
V
SENSE(MAX)
voltage of 75mV. The calculated V
ITH
scale
factor with a 0.003
Ω
sense resistor is:
V
Scale Factor
V
Range Sense
sistor Value
V
V
V
V
V A
ITH
ITH
SENSE MAX
=
∆
=
=
•
Re
( .
– .
) • .
.
.
/
(
)
2 4
0 3
0 003
0 075
0 084
V
ITH
at any load current is:
V
I
I
V
Scale Factor
V
Offset
ITH
OUT DC
L
ITH
ITH
=
+ ∆
+
(
)
•
2
At full load current:
V
A
A
V A
V
V
ITH MAX
P P
(
)
• .
/
.
.
=
+
+
=
−
15
5
2
0 084
0 3
1 77
At minimum load current:
V
A
A
V A
V
V
ITH MIN
P P
(
)
.
• .
/
.
.
=
+
+
=
−
0 2
2
2
0 084
0 3
0 40
In this circuit, V
ITH
changes from 0.40V at light load to
1.77V at full load, a 1.37V change. Notice that
∆
I
L
, the
peak-to-peak inductor current, changes from light load to
full load. Increasing the DC inductor current decreases the
permeability of the inductor core material, which de-
creases the inductance and increases
∆
I
L
. The amount of
inductance change is a function of the inductor design.
To create the 30mV input offset, the gain of the error
amplifier must be limited. The desired gain is:
A
V
Input Offset
V
V
V
ITH
=
∆
=
=
1 37
2 0 03
22 8
.
( .
)
.
Connecting a resistor to the output of the transconductance
error amplifier will limit the voltage gain. The value of this
resistor is:
R
A
Error Amplifier g
ms
k
ITH
V
m
=
=
=
22 8
1 3
17 54
.
.
.
To center the output voltage variation, V
ITH
must be
centered so that no I
TH
pin current flows when the output
voltage is nominal. V
ITH(NOM)
is the average voltage be-
tween V
ITH
at maximum output current and minimum
output current:
V
V
V
V
V
V
V
V
ITH NOM
ITH MAX
ITH MIN
ITH MIN
(
)
(
)
(
)
(
)
–
.
– .
.
.
=
+
=
+
=
2
1 77
0 40
2
0 40
1 085
The Thevenin equivalent of the gain limiting resistance
value of 17.54k is made up of a resistor R5 that sources
current into the I
TH
pin and resistor R1 that sinks current
to SGND.
APPLICATIO S I FOR ATIO
W
U
U
U
