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LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
7. Device Information
1. PIN ASSIGNMENT (TOP VIEW)
2. Pin List
PIN NAMES
FLASH MEMORY
A0 to A22
Address inputs for Pseudo SRAM & Nor Flash Memory
DQ0 to DQ15
Data inputs / outputs for Pseudo SRAM & Nor Flash Memory
I/O1 to I/O8
Data inputs / outputs for Nand E
2
PROM
CE1ps
, CE2ps
Chip enable inputs for Pseudo SRAM
CEf
Chip enable inputs for Nor Flash Memory
CEn
Chip enable inputs for Nand E
2
PROM
OE
Output enable input for Pseudo SRAM & Nor Flash Memory
WE
Write enable input for Pseudo SRAM & Nor Flash Memory
REn
Read enable input for Nand E
2
PROM
WEn
Write enable input for Nand E
2
PROM
LB, UB
Data byte control input for Pseudo SRAM
CLE
Command latch enable input for Nand E
2
PROM
ALE
Address latch enable input for Nand E
2
PROM
WP/ACC
Write protect/program acceleration input for Nor Flash Memory
WPn
Write protect input for Nand E
2
PROM
RESET
Hardware reset input for Nor Flash Memory
RY/BYf
Ready/Busy output for Nor Flash Memory
RY/BYn
Ready/Busy output for Nand E
2
PROM
V
CCps
Power supply for Pseudo SRAM
V
CCf
Power supply for Nor Flash Memory
V
CCn
Power supply for Nand E
2
PROM
V
SS
Ground
NC
Not connected