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3. TECHNICAL BRIEF
GS290 Operational Description Revision B
LG Electronics
40/136
LGE Property
3.6. Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with 8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29).
The 512Mbit Nand Flash memory with DDRAM stacked device family offers multiple high-performance
solutions.
Figure 9 Flash memory & DDR RAM MCP circuit diagram
n0
1
53
1
C
04
1
C
n0
1
n0
1
44
1
C
64
1
C
n0
1
K3.
3
50
1
R
TP103
u1.
0
91
1
C
SD_1V8
40
1
R
K0
1
u1.
0
90
1
C
92
1
C
u1.
0
SD_1V8
SD_1V8
TP106
TP108
TP109
TP112
TP104
81
1
C
n0
1
u1.
0
14
1
C
54
1
C
u1.
0
63
1
C
u1.
0
n0
1
73
1
C
K522H1HACB-B060
U101
21
T
11
T
01
T
3T
2T
1T
21
R
11
R
01
R
3
R
2
R
1
R
21
P
11
P
3
P
2
P
1
P
2
N
2
M
2L
01
K
9
K
8
K
5
K
4
K
2
K
11
J
01
J
9J
8J
7J
6J
5J
4J
3J
P8
D5
P4
D6
E6
P6
F6
C8
F5
C4
E5
D7
P5
C7
C6
P9
L7
P7
L6
H10
K7
G2
K6
C9
N9
C5
M9
L9
H2
N8
M8
N3
L8
E3
N7
K3
M7
L3
N6
F3
M6
M3
N5
G3
M5
L5
D11
N4
E11
M4
F11
L4
G11
E9
K11
E7
L11
F7
M11
G5
N11
G7
C10
D9
D10
D8
E10
E8
F10
F8
L10
G8
M10
G4
N10
F4
P10
E4
D4
2J
9
H
8
H
7
H
6
H
5
H
4
H
3
H
01
G
9
G
6
G
9F
2F
11
H
2
E
3
D
2
D
1
D
21
C
11
C
3
C
2
C
1
C
21
B
11
B
01
B
3
B
2
B
1
B
21
A
11
A
01
A
3
A
2
A
1
A
1
C
N
2
C
N
3
C
N
4
C
N
5
C
N
6
C
N
7
C
N
8
C
N
9
C
N
01
C
N
11
C
N
21
C
N
31
C
N
41
C
N
51
C
N
61
C
N
71
C
N
81
C
N
91
C
N
02
C
N
12
C
N
22
C
N
32
C
N
42
C
N
52
C
N
62
C
N
72
C
N
82
C
N
92
C
N
03
C
N
13
C
N
23
C
N
33
C
N
43
C
N
53
C
N
A0
A1
I_O0
A2
I_O1
A3
I_O2
A4
I_O3
A5
I_O4
A6
I_O5
A7
I_O6
A8
I_O7
A9
I_O8
A10
I_O9
A11
I_O10
A12
I_O11
A13
I_O12
DQ0
I_O13
DQ1
I_O14
DQ2
I_O15
DQ3
DQ4
_CE
DQ5
_WEN
DQ6
_RE
DQ7
ALE
DQ8
CLE
DQ9
R__B
DQ10
_WP
DQ11
DQ12
VCCN1
DQ13
DQ14
VSS1
DQ15
VSS2
LDQM
VSS3
UDQM
VSS4
LDQS
VSS5
UDQS
VSS6
_CLK
CLK
VSSQ
CKE
BA0
VDD1
BA1
VDD2
_RAS
VDD3
_CAS
_WED
VDDQ1
_CS
VDDQ2
63
C
N
73
C
N
83
C
N
93
C
N
04
C
N
14
C
N
24
C
N
34
C
N
44
C
N
54
C
N
64
C
N
74
C
N
84
C
N
94
C
N
05
C
N
15
C
N
25
C
N
35
C
N
45
C
N
55
C
N
65
C
N
75
C
N
85
C
N
95
C
N
06
C
N
16
C
N
26
C
N
36
C
N
46
C
N
56
C
N
66
C
N
76
C
N
86
C
N
96
C
N
07
C
N
TP102
TP107
ADD[29]
DATA[10]
DATA[15]
DATA[13]
DATA[12]
DATA[11]
DATA[9]
DATA[8]
DATA[2]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[1]
DATA[0]
UDQS
LDQS
ADD[28]
ADD[27]
ADD[26]
SDCLKI
_WR
_WR
SDCLKO
_RD
_RAM_CS
CKE
_CAS
FCDP
_BC1
_BC0
_NAND_CS
ADD[25]
ADD[4]
ADD[3]
ADD[24]
ADD[23]
ADD[22]
ADD[21]
ADD[20]
ADD[2]
ADD[19]
ADD[18]
ADD[17]
ADD[17]
ADD[16]
ADD[16]
ADD[9]
ADD[8]
ADD[13]
ADD[7]
ADD[12]
ADD[6]
ADD[11]
ADD[5]
ADD[10]
ADD[1]
ADD[0]
_RAS
ADD[15]
ADD[14]
DATA[14]
BA0
BA1
_WP
ADD[16:29]
ADD[0:15]
DATA[0:15]
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
Large Block Memory
GS290 Operational Description Revision B
LG Electronics
40/136
LGE Property
3.6. Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on GS290 with 8 & 16 bit parallel data bus thru ADD(0) ~ ADD(29).
The 512Mbit Nand Flash memory with DDRAM stacked device family offers multiple high-performance
solutions.
Figure 9 Flash memory & DDR RAM MCP circuit diagram