LG GB175, Service Manual, Page: 21 / 158

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High resolution D/A Converters for Stereo Audio playback
Stereo analog input for stereo audio source
Analog multiplexer for Stereo Audio
Stereo to Mono Conversion
FM radio recording
3.1.5 General Description
Figure 3-1-2 details the block diagram of MT6225. Based on dual-processor architecture, the
major processor of MT6225 is ARM7EJ-S, which mainly runs high-level GSM/GPRS protocol
software as well as multi-media applications. With the other one is a digital signal processor
corresponding for handling the low-level MODEM as well as advanced audio functions. Except
for some mixed-signal circuitries, the other building blocks in MT6225 are connected to either the
microcontroller or the digital signal processor. Specifically, MT6225 consists of the following
subsystems:
Microcontroller Unit (MCU) Subsystem, including an ARM7EJ-S RISC processor and its
accompanying memory management and interrupt handling logics.
Digital Signal Processor (DSP) Subsystem, including a DSP and its accompanying memory,
memory controller, and interrupt controller.
MCU/DSP Interface, where the MCU and the DSP exchange hardware and software
information.
Microcontroller Peripherals, which include all user interface modules and RF control interface
modules.
Microcontroller Coprocessors, which intend to run computing-intensive processes in place of
Microcontroller.
DSP Peripherals, which are hardware accelerators for GSM/GPRS channel codec.
Multi-media Subsystem, which integrate several advanced accelerators to support multi-media
applications.
Voice Front End, the data path of conveying analog speech from and to digital speech.
Audio Front End, also the data path of conveying stereo audio from stereo audio source
Baseband Front End, the data path of conveying digital signal from and to analog signal of RF
modules.
Timing Generator, generating the control signals related to the TDMA frame timing.
Power, Reset and Clock subsystem, managing the power, reset and clock distribution inside
MT6225.