LG GB175, Service Manual, Page: 18 / 158

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Overall, MT6225’s audio features provide a rich platform for multi-media applications.
MT6225 GSM/GPRS Baseband Processor Data Sheet 1.12
Radio Interface
MT6225 integrates a mixed-signal Baseband front-end in order to provide a well-organized
radio interface with flexibility for efficient customization. It contains gain and offset calibration
mechanisms, and filters with programmable coefficients for comprehensive compatibility control
on RF modules. This approach also allows the usage of a high resolution D/A Converter for
controlling VCXO or crystal, thus reducing the need for expensive TCVCXO. MT6225 achieves
great MODEM performance by utilizing 14-bit high resolution A/D Converter in the RF downlink
path. Furthermore, to reduce the need for extra external current-driving component, the driving
strength of some BPI outputs is designed to be configurable.
Debug Function
The JTAG interface enables in-circuit debugging of software program with the ARM7EJ-S core.
With this standardized debugger interface, the MT6225 provides developers with a wide set of
options for choosing ARM development kits from supports of thirty parties. For
security reason, JTAG interface can be disabled by programming internal OTP (one-time
programmable) fuse.
Power Management
The MT6225 offers various low-power features to help reduce system power consumption.
These features include Pause Mode of 32KHz clocking at Standby State, Power Down Mode for
individual peripherals, and Processor Sleep Mode. In addition, MT6225 is also fabricated in
advanced low leakage CMOS process, hence providing an overall ultra low leakage solution.
Package
The MT6225 device is offered in a 12mm×12mm, 264-ball, 0.65 mm pitch, TFBGA package.
3.1.2 Platform Feature
General
Integrated voice-band, audio-band and base-band analog front ends
TFBGA 12mm×12mm, 264-ball, 0.65 mm pitch package
MCU Subsystem
ARM7EJ-S 32-bit RISC processor
High performance multi-layer AMBA bus
Java hardware acceleration for fast Java-based games and applets
ARM7EJ-S Operating frequency: 26/52/104 MHz
Dedicated DMA bus
14 DMA channels
48K Bytes on-chip SRAM
72K Bytes MCU dedicated Tightly Coupled Memory
16K Bytes Code cache
On-chip boot ROM for Factory Flash Programming
Watchdog timer for system crash recovery
2 sets of General Purpose Timer
Circuit Switch Data coprocessor
Division coprocessor
External Memory Interface
Supports up to 3 external devices
Supports 16-bit memory components with maximum size of up to 64M Bytes each
Supports Mobile RAM and Cellular RAM
Supports Flash and SRAM with Page Mode or Burst Mode
Supports Pseudo SRAM