20
Pin No.
Symbol
I/O
Description
41
DA08
O
1, 0
Outputs DA8 when PSSL=1, or GFS when PSSL=0.
42
DA07
O
1, 0
Outputs DA7 when PSSL=1, or RFCK when PSSL=0.
43
DV
DD
2
Digital Power supply
44
DA06
O
1, 0
Outputs DA6 when PSSL=1, or C2PO when PSSL=0.
45
DA05
O
1, 0
Outputs DA5 when PSSL=1, or XRAOF when PSSL=0.
46
DA04
O
1, 0
Outputs DA4 when PSSL=1, or MNT3 when PSSL=0.
47
DA03
O
1, 0
Outputs DA3 when PSSL=1, or MNT2 when PSSL=0.
48
DA02
O
1, 0
Outputs DA2 when PSSL=1, or MNT1 when PSSL=0.
49
DA01
O
1, 0
Outputs DA1 when PSSL=1, or MNT0 when PSSL=0.
50
DV
SS
2
Digital GND
51
XTSL
I
X'tal selection input
52
MCKO
O
1, 0
Clock output. Inverse output of XTLI
53
FSTI
I
2/3 frequency demultiplication input of MCLK
55
FSTO
O
1, 0
2/3 frequency demultiplication output. Unaffected by vari-pitch
56
C4M
O
1, 0
1/4 frequency demultiplication output. Affected by vari-pitch
57
C16M
O
1, 0
16.9344MHz output. Subject to vari-pitch control.
58
DV
DD
3
Digital power supply
59
MD2
I
Digital-Out ON/OFF control. "H" for ON, "L" for OFF.
60
DOUT
O
1, 0
Digital-Out output.
61
MUTE
I
"H" for muting, "L" for release.
62
WFCK
O
1, 0
WFCK (Write Frame Clock) output.
63
SCOR
O
1, 0
"H" when subcode Sync S0 or S1 is detected.
64
SBSO
O
1, 0
Serial output of Sub P to W
65
EXCK
I
Clock input for reading SBSO
66
SQSO
O
1, 0
Outputs 80-bit Sub Q and 16-bit PCM peak-level data.
67
SQCK
I
Clock input for reading SQSO
68
SCSY
I
Input of GRSCOR
69
XRST
I
System reset. "L" for resetting
70
DTS2
I
Test pin for DAC. Normally "H"
75
DTS1
I
Test pin for DAC. Normally "H"
76
DTS0
I
Test pin for DAC. Normally "L"
77
XWO
I
Window open input for DAC synchronization. generally, at "L" window open
78
DAS0
I
Test pin for DAC. Normally "H"
79
DAS1
I
Test pin for DAC. Normally "L"
80
DV
SS
3
Digital GND
81
DV
SS
4
Analog GND
82
AO2R
O
1, 0
CH2•DAC•PWM output (reverse phase)
