IC501 CXD3000R
Pin Description
19
Pin No.
Symbol
I/O
Description
3
SE
I
Slide Error input
4
FE
I
Focus Error input
5
VC
I
Center voltage input
6
VPCO1
O
1, Z, 0
Output of VCO2 charge pump for vari-pitch PLL
7
VPCO2
O
1, Z, 0
Output 2 of VCO2 charge pump for vari-pitch PLL
8
VCTR
I
Input of VCO2 control voltage for vari-pitch EFM
9
FILO
O
Analog
Output of Filter for master PLL (slave = digital PLL)
10
FILI
I
Input to filter for master PLL
11
PCO
O
1, Z, 0
Output of charge pump for master PLL
12
CLTV
I
VCO control voltage lnput for master PLL
13
A V
SS
1
Analog GND
14
RFAC
I
EFM signal input
15
BIAS
I
Asymmetry circuit constant current input
16
ASYI
I
Asymmetry comparator circuit voltage input
17
ASYO
O
1, 0
EFM full-swing output
18
A V
DD
1
Analog power supply
20
D V
DD
1
Digital power supply
21
D V
SS
1
Digital GND
22
ASYE
I
Asymmetry circuit ON/OFF (L=OFF, H=ON)
23
PSSL
I
Input used to switch the audio data output mode. (L=serial, H=parallel)
24
WDCK
O
1, 0
D/A interface for 48-bit slot. Word clock f=2Fs
25
LRCK
O
1, 0
D/A interface for 48-bit slot. LR clock f=Fs
26
LRCKI
I
LR clock input to DAC (48-bit slot)
27
DA16
O
1, 0
Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot (2's complements,
MSB first) when PSSL=0.
28
PCMDI
I
Audio data input to DAC (48-bit slot)
29
DA15
O
1, 0
Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.
30
BCKI
I
Bit clock input to DAC (48-bit slot)
31
DA14
O
1, 0
Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2's complements,
LSB first) when PSSL=0.
32
DA13
O
1, 0
Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.
33
DA12
O
1, 0
Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.
34
DA11
O
1, 0
Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
39
DA10
O
1, 0
Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
40
DA09
O
1, 0
Outputs DA9 when PSSL=1, or XPLCK when PSSL=0.
