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readout proceeds at 100 nsec per hit. In Common Stop Single Word
mode, the offset is subtracted, the data is shifted to adjust the resolution,
and the correct number of bits are inserted into the output data word.
Valid data is stored in the event buffer. This takes place in a three stage
pipeline inside the Xilinx chip. While this pipeline is starting up, the
header word is written into the event buffer. When all MTD133s have
been unloaded a tag word is written into the event buffer to separate
events. Similar sequences occur for the three other operating modes.
EVENT BUFFER MEMORY
The buffer memory is supplied by two 9 by 8192 FIFO chips. Sixteen bits
are used for the data, and one bit as a tag to separate events in the
FIFO. Writing to the FIFO is done by the MTD readout, or by the
CAMAC interface for testing. The half full flag is used to block further
events by keeping the BUSY on. When enough data has been read to
reduce the FIFO below half full, the BUSY will become false. Readout
from the FIFO is either by CAMAC or the ECL port. A separate FIFO,
located inside the Xilinx chip records the data status (some or none) for
each event, to facilitate header suppression. An event counter, also
located inside the Xilinx chip keeps track of the number of complete
events stored in the FIFO.
CAMAC INTERFACE
The CAMAC interface uses a PAL to provide the startup sequence of
loading the Xilinx chip with one of 4 programs stored in an EPROM. After
programming, the PAL is disabled (except for F30) and all CAMAC
decoding is done inside the Xilinx chip. The CAMAC data path is 16 bits
bidirectional to the Xilinx chip, and 16 bits read only from the event
buffer outputs. A multiplexer is required in the data path to select the
Xilinx or event buffer data source.
ECL PORT
A high speed PAL provides the logic for the WST-WAK handshake, the
REN-PASS logic and the event buffer read pulses. Standard TTL-ECL
level shifters are used to drive the outputs. The pull down resistors on
the outputs are installed in sockets, to allow bussing of the ECL port
connectors into a LeCroy 4301 FERA driver or equivalent.
TRIGGER OUTPUTS
The 32 dECL input signals are OR’ed together in groups of 4 and
converted to 8 TTL signals. These are input to the Xilinx chip. The digital
one shots, digital delay and latch circuits all reside inside the Xilinx chip.
The 8 output signals are converted back to ECL and are available at the
rear panel. An external clock input allows the synchronization of the
digital one shots and delay for multiple 3377 modules.
SUPPORT CIRCUITS
Nearly all control logic for the module is located in the Xilinx program-
mable gate array. Most of the circuitry on the board (except for the
MTD133s) consists of data path and support circuits. The versatility of
this module is entirely due to the large amount of logic which can be
programmed into this gate array chip. This is many times the amount
that can be placed on a CAMAC board using ordinary integrated circuits.
The remaining support circuits on the board consists of power supplies,
level shifters and input signal conditioning.
