26
bit 12
Selects Buffer mode
1 = Multi-event buffer mode
0 = Single buffer mode. In this mode the FERA
readout is compatible with the 4300B FERA ADC.
The request delay (see register 3) must be set
appropriately.
bit 13
Selects Header mode
0 = always have header (default)
1 = skip header if no data words
bit 14, 15
Read only, indicates the program load in use. Common
Start mode is 1
control register 1 (subaddress 1)
bits 0-9
not used, always read 0.
bit 10-11
Selects the Measure Pause Interval (MPI).
0 = no MPI
1 = 800 nsec MPI
2 = 1600 nsec MPI
3 = 3200 nsec
bit 12
MPI Selects FAST FERA mode,
1 = fast
0 = normal
bit 13 - 15
Event serial number. This 3 bit number is in the header
data word. It is incremented after each event. It can be
written and read to allow synchronizing several modules.
It is cleared by CAMAC command F9.
control register 2 (subaddress 2)
bits 0-3
The maximum number of hits allowed per TDC 16 hits.
bits 4-15
Not used, always read 1
control register 3 (subaddress 3)
bits 0-3
The request delay setting. This is used only 4300B FERA
ADC compatible mode. The range is from 0 to
30 microseconds, in 2 microsecond steps. In this mode
the BUSY becomes the FERA request output
bits 4-15
The maximum time range for the data, tested before
shifting and readout, in units of 8 ns. Bit 4 has a value of
8 ns. This enforces a precise common start time out
control register 4 (subaddress 4)
bits 0-9
The Common start time out value in units of 50 nsec, up
to 32 microseconds. The minimum delay is about
25 nsec, for a setting of 0. The actual value jitters
50 nsec due to the synchronization with the internal
50 nsec clock. This MUST be set to a value LESS THAN
full scale (32,767.5 microseconds).
