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The common start time out value from register 4 controls the end of
acquisition in steps of 50 nsec, with a 50 nsec jitter due to clock
synchronization. This value should be set to result in a minimum time out
slightly longer than the value specified in register 3. If the external
common stop time out is used, there is no synchronization jitter, and the
coincidence resolution can be set precisely.

For example, with 2 nsec resolution and leading edge mode, the maxi-
mum time can be as large as 2046 nsec. The time out should be set to
41 (2050 nsec), and the offset value to 2048. This allows use of the full
available range.

NOTE:

Any data which occurs after the enforced Common Start timeout

time, but before the actual end of acquisition (the common start time out)
will still be recorded. This data will occupy storage space in the MTD133
chip. It is recommended to set the maximum number of hits to a value
slightly higher than the number expected.

Dead Time

After the common start time out the 3377 buffers the data. Buffering
takes typically 1.8

µ

s +100 nsec per hit. During this time the front panel

BUSY output is asserted and the module responds with Q=1 to an F27,
A1 command. Any inputs received at the front panel will be ignored
during this period. Only when buffering of the data is complete and the
BUSY is turned off is the module ready to receive data at the front panel
signal inputs. The module is now ready for a new event, beginning with
the common hit. If the 3377 is not set to buffer (see section “Buffered
Mode”) then busy will remain on until the data is read out of the unit.

Front Panel Clear

This input is used to clear an event in progress. The CLEAR signal is
synchronized internally with the 100 nsec system clock, and its behavior
exhibits 100 nsec of jitter due to the random phase of this clock with
respect to the external input signals.

The CLEAR is effective from COMMON START to the end of MPI. If
MPI is set to 0, then CLEAR is effective from COMMON START to the
COMMON START TIME OUT. Note that the COMMON START TIME
OUT period is effectively an ‘MPI’. Note that CLEAR is ALWAYS permit-
ted during the COMMON START TIME OUT period. To be reliable, the
CLEAR must arrive at least 100 nsec AFTER the leading edge of the
COMMON START, and at least 100 nsec BEFORE the COMMON
START TIME OUT or the end of MPI (COMMON START TIME OUT plus
the MPI setting).

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Summary of Contents for 3377

Page 1: ...1 OPERATOR S MANUAL MODEL 3377 32 CHANNEL CAMAC TDC Revised January 1997 ECO 1101 ...

Page 2: ...10977 6499 Tel 914 578 6013 Fax 914 578 5984 E mail lrs_support lecroy com Copyright December 1997 LeCroy is a registered trademark of LeCroy Corporation All rights reserved Information in this publication supersedes all earlier versions Specifications are subject to change ...

Page 3: ...user acting as the system integrator to ensure that the overall system is CE compliant This product was demonstrated to meet CE conformity using a CE compliant crate housed in an EMI RFI shielded enclosure It is strongly recommended that the system integrator establish these same conditions CE CONFORMITY ...

Page 4: ...ecification SPECIFICATIONS The information contained in this manual is subject to change without notice The reference for product specification is the Technical Data Sheet effective at the time of purchase ELECTROSTATIC SENSITIVITY While measures have been taken to protect the MTD133 ASIC from electrostatic damage it is still imperative to follow anti static procedures when handling this CMOS devi...

Page 5: ...6 Standard CAMAC Function Codes 16 4 Operating Instructions Programming the Unit for a Different Mode of Operation 19 Operating Modes 20 Mode 0 Common Stop Single Word Mode 21 Control Registers 21 Maximum Time Range 23 Offset 23 Dead Time 24 Front Panel Clear Input 24 Mode 1 Common Start Single Word 25 Control Registers 25 Common Start Time Out 27 Dead Time 28 Front Panel Clear 28 Mode 2 Common St...

Page 6: ... FERA Behavior 39 4300 Compatible Mode 39 Fast FERA Mode 40 Data Formats 40 Single Word Format 40 Double Word Format 40 Suppressing the Header 41 Example 3377 Programming Sequence 42 5 Theory of Operation Time Measurements 43 Control and Readout 43 Event Buffer Memory 44 CAMAC Interface 44 ECL Port 44 Trigger Outputs 44 Support Circuits 44 6 Additional Information Testing the Model 3377 45 Extendi...

Page 7: ...n authorized service facility within the warranty period provided that the warrantor s examination discloses that the product is defective due to workmanship or materials and has not been caused by misuse neglect accident or abnormal conditions or operations The purchaser is responsible for the transportation and insurance charges arising from the return of products to the servicing facility LeCro...

Page 8: ...ram for your use on a single machine Transfer the software and the license to another party if the other party accepts the terms of this agreement and you relinquish all copies whether in printed or machine readable form including all modified or merged versions SERVICE PROCEDURE Products requiring maintenance should be returned to the Customer Service Department or authorized service facility If ...

Page 9: ... edge connector on the module should mate with the bus connector with modest pressure The thumb screw located on the lower edge of the card should be engaged and tightened Note the slot number of the module as it will later be used for addressing CABLES The 3377 is designed to use twisted pair cables for the input output and control signals single twisted pair cables for the control inputs and 34 ...

Page 10: ...d output format The single word format packs 10 data bits leading edge only 9 bits if both edges are recorded into a 16 bit word for low dead time drift chamber applications The programmable offset and resolution 500 ps to 4 nsec LSB allow the time range 255 nanoseconds to 4 microsec onds to be placed as a window anywhere within the 32 microsecond full scale The double word format preserves the fu...

Page 11: ...ard Changing the mode Common Start Stop single double word requires a series of simple CAMAC commands which clear and repro gram the Xilinx gate array with the appropriate firmware from an on board EPROM SPECIFICATIONS Please refer to the Module 3377 technical data sheet for a complete summary of the current specifications FRONT PANEL The LeCroy Module 3377 TDC front panel provides the user with c...

Page 12: ...quisition in common start mode It is OR ed with the internal time out WST Write Strobe dECL output indicates when a valid data word is present on the ECLport BSY Busy output This dECL output indicates the 3377 cannot accept hits This occurs during the buffering dead time and when the multievent buffer is full CLR Clear input A dECL input used to fast clear events and abort acquisition or MTD133 re...

Page 13: ... output 3 ch 8 11 4 7 8 Trigger output 4 ch 12 15 5 9 10 Trigger output 5 ch 16 19 6 11 12 Trigger output 6 ch 20 23 7 13 14 Trigger output 7 ch 24 27 8 15 16 Trigger output 8 ch 28 31 9 pins 17 18 Output disable enabled when open 10 pins 19 20 External trigger clock input STANDARD CAMAC FUNCTION CODES F0 A0 Read FIFO data until end of event Q 1 for valid data Q 0 at end F0 A1 Read FIFO data alway...

Page 14: ...following commands that are available only during the programming mode of the Model 3377 s internal Xilinx logic chip These enable the mode to be set by selecting a firmware program from the 4 that are installed in the EPROM or loading a different program from CAMAC For these commands the A lines are not decoded they are simply ignored F9 Clear data buffers enable Xilinx program F12 Test if Xilinx...

Page 15: ...initially powered on the module configures itself for Common Stop Single Word mode The module is ready for the first command approximately 200 milliseconds after power on The first command received by the module must be F9 for correct operation To change to any other mode the following sequence of CAMAC opera tions to the module is required 1 F30 any subaddress This selects programming mode and re...

Page 16: ...d by the PAL except for F30 which starts the reprogramming sequence The F9 command also MUST be the FIRST command received by the module after power up to ensure that the PAL has been disabled After loading the Xilinx gate array and performing the F9 command the Xilinx gate array takes control of the module The new CAMAC function codes which have been programmed into the gate array logic become op...

Page 17: ... mode 0 Single buffer mode In this mode the FERA readout is compatible with the 4300B FERA ADC The request delay see register 3 must be set appropriately default bit 13 Selects Header mode 0 always have header default 1 skip header if no data words User settable ID Code Control Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Shift Value Edge Recording Readout Mode Buffer Mode Header Mode Mod...

Page 18: ...s incremented after each event It can be written and read to allow synchronizing several modules It is cleared by CAMAC command F9 Default is 0 control register 2 subaddress 2 bits 0 3 The maximum number of hits allowed per TDC channel from 1 to 16 A value of zero selects 16 hits Default is 15 bits 4 15 The maximum full scale time allowed for the TDC data in units of 8 nsec from 0 to 32767 5 nsec ...

Page 19: ...are compared to the upper 12 bits of the data words inside the MTD133 The lower 4 bits are ignored by the hardware inside the MTD133 The maximum data value which can be readout is equal to the maximum time range value 15 counts or a multiple of 8 nsec 7 5 nsec A value of zero for the upper 12 bits allows readout of all data words of 15 counts 7 5 nsec or less Offset The Offset register is implemen...

Page 20: ...rted and the module responds with Q 1 to an F27 A1 command Any inputs received at the front panel will be ignored during this period Only when buffering of the data is complete and the BUSY is turned off is the module ready to receive data at the front panel signal inputs The trigger system must wait for the pipeline to refill before sending a new common stop signal This refill time should be equa...

Page 21: ...egister 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 User settable ID code Data Shift Value Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FERA Mode Not used MPI Serial number Control Register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used Max hits Control Register 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Enforced Common Start Time Out...

Page 22: ...low synchronizing several modules It is cleared by CAMAC command F9 control register 2 subaddress 2 bits 0 3 The maximum number of hits allowed per TDC 16 hits bits 4 15 Not used always read 1 control register 3 subaddress 3 bits 0 3 The request delay setting This is used only 4300B FERA ADC compatible mode The range is from 0 to 30 microseconds in 2 microsecond steps In this mode the BUSY becomes...

Page 23: ...in buffered mode 4 000BH time out at 550 nsec slightly longer than the enforced time out delay 5 0000H test mode NOT selected Common Start Time Out A precise common start time out is enforced in steps of 8 nsec by the value in control register 3 bits 4 15 The raw data value is compared to this value Any data value GREATER THAN or EQUAL TO the timeout value will be discarded Only data LESS THAN the...

Page 24: ... the front panel BUSY output is asserted and the module responds with Q 1 to an F27 A1 command Any inputs received at the front panel will be ignored during this period Only when buffering of the data is complete and the BUSY is turned off is the module ready to receive data at the front panel signal inputs The module is now ready for a new event beginning with the common hit If the 3377 is not se...

Page 25: ...r mode In this mode the FERA readout is compatible with the 4300B FERA ADC The request delay see register 3 must be set appropriately default bit 13 Selects Header mode 0 always have header default 1 skip header if no data words Mode 2 Control Registers Control Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 User settable ID code Not used Edge Recording Readout Mode Buffer Mode Header Mode Mode C...

Page 26: ...ta word It is incremented after each event It can be written and read to allow synchronizing several modules It is cleared by CAMAC command F9 Default is 0 control register 2 subaddress 2 bits 0 3 The maximum number of hits allowed per TDC channel from 1 to 16 A value of zero selects 16 hits Default is 15 bits 4 15 The maximum full scale time allowed for the TDC data in units of 8 nsec from 0 to 3...

Page 27: ...it During this time the front panel BUSY output is asserted and the module responds with Q 1 to an F27 A1 command Any inputs received at the front panel will be ignored during this period Only when buffering of the data is complete and the BUSY is turned off is the module ready to receive data at the front panel signal inputs The trigger system must wait for the pipeline to refill before sending a...

Page 28: ...e FERA readout is compatible with the 4300B FERA ADC The request delay see register 3 must be set appropriately Control Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 User settable ID code Not Used Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FERA Mode Not used MPI Serial number Control Register 2 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 29: ...its 0 3 The maximum number of hits allowed per TDC channel from 1 to 16 A value of zero selects 16 hits bits 4 15 Not used always reads 1 control register 3 subaddress 3 bits 0 3 The request delay setting This is used only in 4300B FERAADC compatible mode The range is from 0 to 30 microseconds in 2 microsecond steps bits 4 15 Not used always read 0 control register 4 subaddress 4 bits 0 9 The Comm...

Page 30: ...8 µs 200 nsec per hit During this time the front panel BUSY output is asserted and the module responds with Q 1 to an F27 A1 command Any inputs received at the front panel will be ignored during this period Only when buffering of the data is complete and the BUSY is turned off is the module ready to receive data at the front panel signal inputs The module is now ready for a new event beginning wit...

Page 31: ...35 CLEAR must arrive at least 100 nsec AFTER the leading edge of the COMMON START and at least 100 nsec BEFORE the COMMON START TIME OUT or the end of MPI COMMON START TIME OUT plus the MPI setting ...

Page 32: ...iod or an external clock which must be less than 40 MHz The differential ECL external clock input is on the trigger connector pins 19 and 20 The one shot is retriggerable after one full clock period after the input trigger If a second trigger arrives during an output pulse the output pulse is extended The pipeline delay is adjustable from 0 to 15 clock periods using the same clock as the one shot ...

Page 33: ...ased to cover the random phase of the clocks in each 3377 module Trigger Outputs in the Common Start Modes The eight prompt OR outputs are used as the clock input to flip flops which are enabled by the common START signal and disabled by the end of acquisition the common start time out Any signal inputs during this interval set the flip flop and are latched Signals which arrive before the common S...

Page 34: ...the data and the BUSY signal is the same as for CAMAC readout This mode is NOT COMPATIBLE with 4300B FERA ADC modules The ECLbus must consist only of 3377 or 3377 compat ible modules Standard FERA modules may not be intermixed Unbuffered mode This mode IS COMPATIBLE with the original FERA modules The 4300B ADC modules must be installed first in the ECLbus closer to the 4301 FERA driver The BUSY si...

Page 35: ...ffer which can hold as many as 31 events Fortunately the 3377 can also be operated in an unbuffered mode which although slightly different than the 4300B FERA ADC is quite compatible with it In the multi buffer mode REN is used as a token to read out one event from each 3377 As soon as conversion starts BUSY REQ is asserted BUSY is removed as soon as the event is safely stored in the buffer If REN...

Page 36: ... Format The output data consists of a header word followed by up to 512 data words An event with no data consists of only the header word If header suppression is selected an event with no data results in zero words HEADER bits 0 7 the 8 bit module ID from register 0 bits 8 9 the 2 bit resolution value from register 0 bit 10 the leading both edge recording bit from register 0 0 leading only 1 both...

Page 37: ... 9 identifies edge 0 leading 1 trailing bits 10 14 5 bit channel number SUPPRESSING THE HEADER The Header mode bit register 0 bit 13 when set to 1 allows suppress ing the header word if there is no data in the event This is effective in all readout modes single or double word buffered or unbuffered CAMAC or FERA The event is not suppressed only the header so the event ordering remains correctly sy...

Page 38: ...heck programming complete F9 any subaddress reset PAL Step 2 Initialize module for Common Start example F17 A0 data 0x10FF F17 A1 data 0x0000 F17 A2 data 0x0000 F17 A3 data 0x03F0 F17 A4 data 0x000B F17 A5 data 0x0101 F1 A0 read back register 0 to check F1 A1 read back register 1 to check F1 A2 read back register 2 to check F1 A3 read back register 3 to check F1 A4 read back register 4 to check F1...

Page 39: ... of LIFO storage Both the depth of the storage and the maximum time range are programmable The data is stored in the LIFO in a grey code format When the data is read out the grey code is converted to binary the Common hit time is subtracted and the time difference is compared to the maximum time This is done in a 3 stage pipeline to increase the readout speed The readout is in channel order and th...

Page 40: ...OM After programming the PAL is disabled except for F30 and all CAMAC decoding is done inside the Xilinx chip The CAMAC data path is 16 bits bidirectional to the Xilinx chip and 16 bits read only from the event buffer outputs A multiplexer is required in the data path to select the Xilinx or event buffer data source ECL PORT A high speed PAL provides the logic for the WST WAK handshake the REN PAS...

Page 41: ...t mode controls the built in test pattern generator Bit 8 must be set to enable test mode this disables the front panel inputs The number of pulses is selected by bits 0 4 from 0 to 31 pulses These pulses are applied to all 32 channels The pulse period is selected with bits 5 and 6 as 100 200 400 or 800 nanoseconds The Common Start time out number of hits and resolution must be set appropriately T...

Page 42: ...set to limit the total to less than 150 300 data words For example 4 hits per channel if all 32 channels are used or 16 hits per channel if 9 or fewer channels are used The dead time to buffer an event a common stop is then less than 32 microseconds while input data is being recorded by the other module Each 3377 can store 31 events or 4000 data words for a total of nearly 2 milliseconds of record...

Page 43: ...provide improved double hit resolution and more hits per channel for fewer channels When using two 3377s in a ping pong mode the EXP mod ules can drive a double termination to provide the identical signals to the TDC modules The EXP module drives the center of a short cable the cable has 3 connectors the two ends connect to the two 3377s This will only work for short cables since the differential ...

Page 44: ...19 38 Displays 15 E ECLbus 15 16 F FERA 38 FERA Compatibility 38 Front Panel 14 I Inputs and Outputs 15 BSY 15 CLR 15 COM 15 PASS 15 REN 15 T O 15 WAK 15 WST 15 Internal Tester 13 L LabView Support 47 M Maintenance Agreements 9 Maximum Time Range 23 31 Measured Pulse Interval MPI 15 24 28 31 34 MTD133 23 28 31 O Offset 23 Operating Modes 20 Mode 0 21 Mode 1 25 Mode 2 29 Mode 3 32 R Readout Modes 3...

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