27
bits 10-15
Not used, always reads 0
control register 5 (subaddress 5)
bits 0-4
The number of pulses generated in test mode. 0-31
pulses, each 1/2 clock period long.
bits 5-6
The test mode clock.
0 = 100 nsec
1 = 200 nsec
2 = 400 nsec
3 = 800 nsec
bit 7
Not used, always reads 0
bit 8
Test enable. This must be 1 for test mode.
bits 9-15
Not used, always reads 0.
A simple example of Common START register setup
0 = 10FFH
buffered mode, CAMAC readout, leading edge only,
0.5 nsec resolution, header always, module ID is 255
1 = 0000H
event numbers starts at zero, no MPI
2 = 0000H
16 hits allowed
3 = 03F0H
time out enforced at 511 nsec, no request delay (not used
in buffered mode)
4 = 000BH
time out at 550 nsec, slightly longer than the enforced
time out delay
5 = 0000H
test mode NOT selected
Common Start Time Out
A precise common start time out is enforced in steps of 8 nsec by the
value in control register 3, bits 4-15. The raw data value is compared to
this value. Any data value GREATER THAN or EQUAL TO the timeout
value will be discarded. Only data LESS THAN the timeout will be read
out. This value MUST be consistent with the resolution and edge mode
chosen, or the data will be ambiguous. The Common Start Timeout
value must be less than that given in the table below.
Resolution
Edge Mode
Time Out Value
0.5 nsec
leading edge only
1024
both edges
512
1.0 nsec
leading edge only
2048
both edges
1024
2.0 nsec
leading edge only
4096
both edges
2048
4.0 nsec
leading edge only
8192
both edges
4096
