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Lauterbach C6000, Manual

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Lauterbach C6000 Manual Download Page 44

C6000 Debugger     |    44

©

1989-2022

   Lauterbach        

 

                   

                            

(1) Further “

<component>

.ATBSource 

<source>

” commands might be needed to describe the full trace data 

path from trace source to trace sink.

 

SYStem.CPU

     

Select the used CPU

Default selection: C64X.

Selects the processor type. If your ASIC is not listed, select the type of the integrated DSP core.

TRACEFUNNELPORT

 

<port>

FUNNEL1.ATBSource ADTF

 

<port>

 (1)

TRACETPIUFUNNELPORT

 

<port>

FUNNEL3.ATBSource ADTF

 

<port>

 (1)

view

state

Format:

SYStem.CPU 

<cpu>

<cpu>

:

C64X 

|

 C6416 

|

 C6455 

|

 C6713 

| …

Summary of Contents for C6000

Page 1: ...MANUAL Release 09 2022 C6000 Debugger...

Page 2: ...et topology 10 parameters describing the DebugPort 16 parameters describing the JTAG scan chain and signal behavior 19 parameters describing a system level TAP MultiTap 23 parameters configuring a Cor...

Page 3: ...rrupts 57 SYStem Option PWRCHECK Check power and clock 57 SYStem Option PWRDWN Allow power down mode 57 SYStem RESetOut Reset target without reset of debug port 57 C64x specific SYStem Commands 58 SYS...

Page 4: ...that are specific for the processor architecture supported by your debug cable To access the manual for your processor architecture proceed as follows Choose Help menu Processor Architecture Manual OS...

Page 5: ...e target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 C...

Page 6: ...and 100 s If a terminal window is open the response time of the trigger system is undefined It is recommended not to use the trigger system and terminal window at the same time Breakpoints Software Br...

Page 7: ...an be used as Read or Write breakpoints Data Value breakpoint Number of on chip data breakpoints that can be used to stop the program when a specific data value is written to an address or when a spec...

Page 8: ...s will make memory accesses possible even when the target CPU is running See SYStem MemAccess and SYStem CpuAccess for more information Examples Memory Class Description P Program Memory D Data Memory...

Page 9: ...tab DebugPort Jtag MultiTap AccessPorts COmponents tab Opens the SYStem CONFIG state window on the specified tab For tab descriptions see below DebugPort default The DebugPort tab informs the debugge...

Page 10: ...ich memory bus and at which base address the debugger can find the control registers of the modules For descriptions of the commands on the COmponents tab see COmponents Format SYStem CONFIG parameter...

Page 11: ...meter AccessPorts AHBAPn Base address AHBAPn HPROT value name AHBAPn Port port AHBAPn RESet AHBAPn view AHBAPn XtorName name APBAPn Base address APBAPn Port port APBAPn RESet APBAPn view APBAPn XtorNa...

Page 12: ...view C5000 C6000 C7000 only parameter COmponents cont CMI Base address CMI RESet CMI TraceID id CMI view COREDEBUG Base address C7000 only COREDEBUG RESet C7000 only COREDEBUG view C7000 only CTI Base...

Page 13: ...EP ATBSource source REP Base address REP Name string REP RESet REP view SC Base address SC RESet SC TraceID id SC view STM Base address STM Mode None SDTI STP STP64 STPv2 STPv2LE STM Name string STM R...

Page 14: ...s ETBBASE address ETBFUNNELBASE address ETFBASE address ETMBASE address parameter Deprecated cont FUNNEL2BASE address FUNNELBASE address HTMBASE address ITMBASE address RTPBASE address SDTIBASE addres...

Page 15: ...on SYStem CPU type to become active and it might additionally depend on further settings Ideally you can select with SYStem CPU the chip you are using which causes all setup you need and you do not ne...

Page 16: ...d might be required in a multicore environment if you use multiple debugger instances multiple TRACE32 PowerView GUIs to simultaneously debug different cores on the same target system Because of the d...

Page 17: ...gCa bleA DebugCableB It specifies which probe cable shall be used e g DebugCableA or DebugCableB At the moment only the CombiProbe allows to connect more than one probe cable Default depends on detect...

Page 18: ...ck on the SWCLK line is stopped kept low You can configure the debugger to pull the SWDIO data line high when no operation is in progress by using SYStem CONFIG SWDPIdleHigh ON Default OFF SWDPTargetS...

Page 19: ...ber of TAPs in the JTAG chain between the TDI signal and the TAP you are describing In BYPASS mode each TAP contributes one data register bit See possible TAP types and example below Default 0 DRPRE b...

Page 20: ...ble 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15...

Page 21: ...mory access changes the JTAG chain and the core TAP position then you can specify the new values with the NEXT parameter After the access for example the parameter NEXTIRPRE will replace the IRPRE val...

Page 22: ...C6000 Debugger 22 1989 2022 Lauterbach...

Page 23: ...the moment the debugger supports three types and its different versions Icepickx STCLTAPx MSMTAP Example DAPTAP tap Specifies the TAP number which needs to be activated to get the DAP TAP in the JTAG...

Page 24: ...ialize the MSMTAP Please note some of these parameters need a decimal input dot at the end IcepickXY means that there is an Icepick version X which includes a subsystem with an Icepick of version Y Fo...

Page 25: ...specially important if the core you intend to debug is connected to such an internal JTAG interface The module controlling these JTAG interfaces is called JTAG Access Port JTAG AP Each JTAG AP can con...

Page 26: ...sed for the HPROT bits in the Control Status Word CSW of a CoreSight AXI Access Port when using the AXI memory class MEMORYAPn HPROT value name Default 0 This option selects the value used for the HPR...

Page 27: ...x3 Cache 0x0 This option configures the value used for the Cache and Domain bits in the Control Status Word CSW 27 24 Cache CSW 14 13 Domain of an Access Port when using the AXI memory class name Desc...

Page 28: ...XtorName name APB bus transactor name identifying the bus where the debug register can be found Used for DAP access class MEMORYAPn XtorName name AHB bus transactor name identifying the bus where syst...

Page 29: ...ss Default port not available DEBUGAPn Port port DEBUGACCESSPORT port deprecated AP access port number 0 255 of a SoC 400 system where the debug register can be found typically on APB Used for DAP acc...

Page 30: ...FIG APBAP1 Base DP 0x80003000 Meaning The control register block of the APB access ports starts at address 0x80003000 AXIAPn Base address This command informs the debugger about the start address of t...

Page 31: ...race components your chip includes and which you intend to use with the debugger s help Each configuration can be done by a command in a script file as well Then you do not need to enter everything ag...

Page 32: ...n most cases Example SYStem CONFIG COREDEBUG Base 0x80010000 0x80012000 SYStem CONFIG BMC Base 0x80011000 0x80013000 SYStem CONFIG ETM Base 0x8001c000 0x8001d000 SYStem CONFIG STM1 Base EAHB 0x2000800...

Page 33: ...e the interconnection by ATBSource source A CoreSight trace FUNNEL has eight input ports port 0 7 to combine the data of various trace sources to a common trace stream Therefore you can enter instead...

Page 34: ...exists only for FUNNELs For a list of possible components including a short description see Components and Available Commands BASE address This command informs the debugger about the start address of...

Page 35: ...ug on a certain chip You will loose trace data at the end of the recording Don t use it if not needed Default OFF RESet Undo the configuration for this component This does not cause a physical reset f...

Page 36: ...om and to the CTIs ARMv8 only ARMV8V3 Channel 0 1 and 2 of the CTM are used to distribute start stop events Implemented on request ARMv8 only ETB Size size Specifies the size of the Embedded Trace Buf...

Page 37: ...just a number which you need to figure out in the chip documentation RTP PerBase address PERBASE specifies the base address of the core peripheral registers which accesses shall be traced PERBASE is n...

Page 38: ...Enables trace to be stored in a dedicated SRAM The trace data will be read out through the debug port after the capturing has finished FUNNEL ATBSource sourcelist FUNNEL Base address FUNNEL Name stri...

Page 39: ...ring statistic data about bus traffic to a system trace module STM Base address STM Mode NONE XTIv2 SDTI STP STP64 STPv2 STM RESet STM Type None Generic ARM SDTI TI System Trace Macrocell STM MIPI ARM...

Page 40: ...ssible via APB bus In an SMP Symmetric MultiProcessing debug session you can enter for the components BMC CORE CTI ETB ETF ETM ETR a list of base addresses to specify one component per core Example as...

Page 41: ...d Available Commands CTICONFIG type Informs about the interconnection of the core Cross Trigger Interfaces CTI Certain ways of interconnection are common and these are supported by the debugger e g to...

Page 42: ...NEL2PORT port FUNNEL2 ATBSource DTM port 1 DTMFUNNELPORT port FUNNEL1 ATBSource DTM port 1 DTMTPIUFUNNELPORT port FUNNEL3 ATBSource DTM port 1 DWTBASE address DWT Base address ETB2AXIBASE address ETB2...

Page 43: ...ess SDTIBASE address STM1 Base address STM1 Mode SDTI STM1 Type SDTI STMBASE address STM1 Base address STM1 Mode STPV2 STM1 Type ARM STMETBFUNNELPORT port FUNNEL4 ATBSource STM1 port 1 STMFUNNEL2PORT...

Page 44: ...trace source to trace sink SYStem CPU Select the used CPU Default selection C64X Selects the processor type If your ASIC is not listed select the type of the integrated DSP core TRACEFUNNELPORT port F...

Page 45: ...le frequency and displays the real value in the SYStem state window Besides a decimal number like 100000 short forms like 10kHz or 15MHz can also be used The short forms imply a decimal value although...

Page 46: ...we offer a different mode ARTCK which does not work as recommended by ARM and might not work on all target systems In ARTCK mode the debugger uses a fixed frequency for TCK independent of the RTCK si...

Page 47: ...rform the memory access Each stop takes some time depending on the speed of the JTAG port the number of the assigned cores and the operations that should be performed Enable CPU deprecated Used to act...

Page 48: ...shall not be debugged or bypassed i e the debugger can access the memory busses such as AXI AHB and APB directly through the memory access ports of the CoreSight DAP Typical use cases The debugger acc...

Page 49: ...d the debugger restores as many debug registers as possible e g on chip breakpoints vector catch events trace control and releases the CPU from reset to start the program execution When a CPU power do...

Page 50: ...used for the Cache and Domain bits in the Control Status Word CSW 27 24 Cache CSW 14 13 Domain of an AXI Access Port of a DAP when using the AXI memory class SYStem Option AXIHPROT Select AXI AP HPROT...

Page 51: ...checked by the debugger SYStem Option DAPREMAP Rearrange DAP memory map The Debug Access Port DAP can be used for memory access during runtime If the mapping on the DAP is different than the processo...

Page 52: ...listed below This is the default Normally it does not hurt to try improper switching sequences Therefore this succeeds in most cases None There is no switching sequence required The SW DP is ready af...

Page 53: ...g Default OFF If enabled the interrupt mask bits of the CPU will be set during assembler single step operations The interrupt routine is not executed during single step operations After single step th...

Page 54: ...GUIs because they cannot access the debug interface anymore To keep the debug interface active it is recommended that SYStem Option DAPDBGPWRUPREQ is set to AlwaysON SYStem Option DAPSYSPWRUPREQ Forc...

Page 55: ...is disabled the debugger will never drive the nRESET nSRST line on the JTAG connector This is necessary if nRESET nSRST is no open collector or tristate signal From the view of the core it is not nec...

Page 56: ...hPriority Set data access priority Default OFF If this option is set to ON the debugger is allowed to stall the CPU pipeline for memory access This will allow to read data more often even during high...

Page 57: ...PWRDWN Allow power down mode Default OFF If this option is OFF the debugger forces the chip to keep clock and keep power on OMAPxxxx devices SYStem RESetOut Reset target without reset of debug port I...

Page 58: ...ion should be used if the debugger shows any unstable behavior SYStem Option TURBO Use DMA for write accesses Default OFF If TURBO is enabled the debugger uses a DMA channel of the DSP to write data t...

Page 59: ...count within AB range Advise the counter to count the specified event only in AB range Alpha and Beta markers are used to specify the AB range Example to measure the time used by the function sieve F...

Page 60: ...his is the default Otherwise an error message is generated TrOnchip RESet Set on chip trigger to default state Sets the TrOnchip settings and trigger module to the default settings Format TrOnchip sta...

Page 61: ...oint to a complex variable the on chip break resources of the CPU may be not powerful enough to cover the whole structure If the option TrOnchip VarCONVert is set to ON the breakpoint will automatical...

Page 62: ...rdware setup refer to the AutoFocus User s Guide autofocus_user pdf Controlling the Trace Capture On the C6x cores the trace capture setup is controlled by the AET command group Trace Breakpoints The...

Page 63: ...is is a standard 20 pin double row connector pin to pin spacing 0 100 in We strongly recommend to use a connector on your target with housing and having a center polarization e g AMP 2 827745 0 A conn...

Page 64: ...input It is connected to the supply translating transceiver nSRST nRESET is used by the debugger to reset the target CPU or to detect a reset on the target It is driven by an open collector buffer A 4...

Page 65: ...JTAG port it is absolutely required that there is a pull down resistor at TCK This is to ensure that TCK is low during a handover between different tools TDO is ICD input only and needs standard TTL...

Page 66: ...C6000 Debugger 66 1989 2022 Lauterbach FAQ Please refer to https support lauterbach com kb...

Page 67: ...C6000 Debugger 67 1989 2022 Lauterbach Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C6000 DSP ICD LA 7838 1 8 3 6 V...

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