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MachXO3-9400 Development Board
Evaluation Board User Guide

© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at

www.latticesemi.com/legal

.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

34

FPGA-EB-02004-1.0

Software Requirements

The following software are required to develop designs for the MachXO3-9400 Development Board:



Diamond 3.9 (or higher)



Diamond Programmer 3.9 (or higher)



LatticeMico System Development Tools

Storage and Handling

Static electricity can shorten the life span of electronic components. Observe these tips to prevent damage that can
occur from electrostatic discharge:



Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband.



Store the development board in the provided packaging.



Touch a metal USB housing to equalize voltage potential between you and the board.

Ordering Information

Table 11.1 Ordering Information

Description

Ordering Part Number

China RoHS Environment-

Friendly Use Period (EFUP)

MachXO3-9400 Development Board

LCMXO3LF-9400C-B-EVN

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...
32
33
34
35
36
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Summary of Contents for MachXO3-940

Page 1: ...MachXO3 9400 Development Board Evaluation Board User Guide FPGA EB 02004 Version 1 0 May 2017 ...

Page 2: ... and Test Connections 14 5 1 Versa Headers 14 5 2 Arduino Board GPIO Headers 16 5 3 FX12 Headers DNI 18 5 4 Aardvark Header DNI 20 5 5 Raspberry Pi Board GPIO Header 21 I2 C and SPI Buses 23 6 1 I2 C Topology 23 6 2 SPI Topology 25 6 2 1 SPI Configuration 25 6 2 2 SPI Flash Access 25 LEDs and Switches 26 7 1 Four Position DIP Switch 26 7 2 General Purpose Push Buttons 27 7 3 General Purpose LEDs 2...

Page 3: ...gn 13 Figure 5 1 Aardvark SS Pin Connections 20 Figure 6 1 I2 C Topology 23 Figure 6 2 I2 C MUX Circuits 24 Figure 7 1 Four Position DIP Switch Circuits 26 Figure 7 2 Four Position DIP Switch Photograph 26 Figure 7 3 Push Button SW5 Circuit Design 27 Figure 7 4 Board LEDs 28 Figure 8 1 POT Circuit Design for VMON7 31 Figure 8 2 POT Wiper Description 31 Figure 8 3 VCC Core Current Monitoring Circui...

Page 4: ...duino J2 Pin Connections 16 Table 5 4 Arduino J3 Pin Connections 17 Table 5 5 Arduino J4 Pin Connections 17 Table 5 6 Arduino J5 Pin Connections 17 Table 5 7 FX12 U4 Header Pin Connections 18 Table 5 8 FX12 U5 Header Pin Connections 19 Table 5 9 Aardvark JP2 Header Pin Connections 20 Table 5 10 Raspberry Pi JP3 Header Pin Connections 21 Table 6 1 I2 C MUX Function 23 Table 6 2 I2 C Global Bus Conn...

Page 5: ...espective holders The specifications and information herein are subject to change without notice FPGA EB 02004 1 0 5 Acronyms in This Document A list of acronyms used in this document Acronym Definition ASC Analog Sense and Control CMOS Complementary Metal Oxide Semiconductor GDDR Graphics Double Data Rate FTDI Future Technology Devices International GPIO General Purpose Input Output I2C Inter Int...

Page 6: ...gns The MachXO3 9400 Development Board is part of the MachXO3 9400 Development Kit which includes the following MachXO3 9400 Development Board pre loaded with the demo design Mini USB cable QuickStart Guide This document is intended to be referenced in conjunction with demo user guides for MachXO3 9400 See the References The contents of this user guide include top level functional descriptions of ...

Page 7: ...g voltage current and temperature monitoring General Purpose Input Output GPIO interface with Arduino and Raspberry Pi boards USB B connection for device programming and Inter Integrated Circuit I2 C utility On board Boot Flash 16 Mbit Serial Peripheral Interface SPI Flash with Quad read feature for user s application 4 position DIP Switches 4 push buttons and 16 LEDs for demo purposes Diamond pro...

Page 8: ...block RAM This device offers a variety of features and programmability For more information on the capabilities of MachXO3 see DS1047 MachXO3 Family Data Sheet 1 4 L ASC10 Device The L ASC10 also referred to as ASC is a Hardware Management Power Thermal and Control Plane Management Expander designed to be used with Platform Manager 2 or MachXO2 MachXO3 FPGAs to implement the Hardware Management Co...

Page 9: ... 5 JP6 DNI Raspberry Pi header JP3 2 4 JP7 DNI Versa header X2 21 R30 DNI Warning Avoid power conflict when the 5 V power path is enabled from the MachXO3 9400 Development Board to the mated board Do Not apply 5V power from both boards when the path is manually shorted Conversely 5 V power can be supplied from onboard headers if J11 is not connected to a USB cable The power from the headers can be...

Page 10: ...ated Board Option Assembly VCC Core R123 DI R127 DNI NA VCCIO0 R124 DI R128 DNI NA VCCIO1 R125 DI R129 DNI R151 DNI for Arduino VCCIO2 R126 DI R130 DNI NA VCCIO3 R132 DI R137 DNI R158 DNI for Raspberry Pi VCCIO4 R133 DI R138 DNI NA VCCIO5 R134 DI R139 DNI NA Note R127 is applicable only in 2 5 V 3 3 V U9 range for LCMXO3LF 9400C device Warning Only one option should be enabled for each MachXO3 dev...

Page 11: ... MachXO3 U3 I2C ASC U7 SPI SPI Flash U6 JTAG Header J1 Raspberry Pi Header JP3 Figure 3 1 JTAG I2 C Programming Architecture 3 1 JTAG Download Interface The MachXO3 9400 Development Board has a built in download controller for programming the MachXO3 device It uses an FT2232H Future Technology Devices International FTDI part to convert USB to JTAG To use the built in download cable connect the USB...

Page 12: ...on between the USB download cable and J1 refer to UG48 Programming Cable User s Guide J1 can also be used as test point when USB to JTAG is working Additionally you can enable the JTAG access path through the Raspberry Pi header JP3 for customer applications This is done by connecting the JP3 header to the J1 header through some onboard resistors The JTAG connections between J1 and JP3 are listed ...

Page 13: ... Clock Frequency Signal Name MachXO3 Ball Location Clock Source Comments 8 MHz ASC_CLK L1 U7 JP1 installed test point TP14 12 MHz 12MHz B10 U1 JP11 installed JP9 removed User defined OSC_IN D22 Y2 DNI JP4 removed and OSC_EN signal MachXO3 ball L20 Logic 1 User defined OSC_IN D22 J10 DNI Y2 not installed or OSC_EN signal MachXO3 ball L20 Logic 0 or JP4 installed Additional information on using opti...

Page 14: ...ers and test connections 5 1 Versa Headers The board provides two headers X2 and X3 for expansion purpose Table 5 1 Versa X2 Header Pin Connections X2 Pin Number Signal Name MachXO3 Ball Location 1 GND 2 NC 3 EXPCON_2V5 4 EXPCON_IO29 E12 5 EXPCON_IO30 D14 6 EXPCON_IO31 C15 7 EXPCON_IO32 C17 8 EXPCON_IO33 D15 9 EXPCON_IO34 C18 10 EXPCON_IO35 D16 11 EXPCON_IO36 C19 12 EXPCON_IO37 D17 13 EXPCON_IO38 ...

Page 15: ...GND 39 EXPCON_3V3 40 GND Notes Signal is optionally connected to power source through resistor DNI Signal is optionally connected to power source through resistor DN Table 5 2 Versa X3 Header Pin Connections X3 Pin Number Signal Name MachXO3 Ball Location 1 HPE_RESOUT G9 2 GND 3 EXPCON_IO0 F8 4 EXPCON_IO1 G8 5 EXPCON_IO2 F9 6 EXPCON_IO3 F7 7 EXPCON_IO4 E7 8 EXPCON_IO5 E6 9 EXPCON_IO6 D5 10 EXPCON_...

Page 16: ...gnal is optionally connected to power source through resistor DN 5 2 Arduino Board GPIO Headers The board provides four headers J2 J3 J4 and J5 for Arduino Zero board adaption Table 5 3 Arduino J2 Pin Connections J2 Pin Number Signal Name Arduino ZERO Board Signal MachXO3 Ball Location Comments 1 AR_IO8 8 U21 2 AR_IO9 9 U22 3 AR_SS_IO10 10 W20 Optional connection to SS through R67 for SPI access D...

Page 17: ...me Arduino ZERO Board Signal MachXO3 Ball Location Comments 1 AR_IO 14 ATN T17 2 NC IOREF 3 AR_RE SET RESET U20 Pin U20 should be set high by default Avoid Arduino ZERO board in Reset status when connected 4 3 3V_ AR 3 3 V 3 3 V power supply from Arduino ZERO board 5 AR_5V 5 V Jump to 5 V main power through JP6 6 GND GND 7 GND GND 8 12V VIN 12 V power supply from Arduino ZERO board Table 5 6 Ardui...

Page 18: ... cables Each header has eight pairs of Low Voltage Differential Signaling LVDS signals for high speed data receiver Table 5 7 FX12 U4 Header Pin Connections U4 Pin Number Signal Name MachXO3 Ball Location 1 CH0_DCK_P AA10 2 CH0_DCK_N AB10 3 GND 4 CH0_DATA0_P AA4 5 CH0_DATA0_N AB4 6 GND 7 CH0_DATA2_P AA5 8 CH0_DATA2_N AB5 9 GND 10 FX_SN 11 FX_SCLK 12 PWR_12V 13 SDA2 AB13 14 SCL2 AA13 15 GND 16 CH2_...

Page 19: ...8 PWR_5 0V 39 SDA1 AA11 40 SCL1 AB11 Notes Signal is optionally connected to power source through resistor DNI 12 V power needs external supply from pin 8 of J4 Table 5 8 FX12 U5 Header Pin Connections U5 Pin Number Signal Name MachXO3 Ball Location 1 CH1_DCK_P AB12 2 CH1_DCK_N AA12 3 GND 4 CH1_DATA0_P AB16 5 CH1_DATA0_N AA16 6 GND 7 CH1_DATA2_P AB17 8 CH1_DATA2_N AA17 9 GND 10 FX_SN 11 FX_SCLK 12...

Page 20: ...hrough USB to a downstream embedded system environment and transfer serial messages using the I2 C and SPI protocols The MachXO3 9400 Development Board provides an Aardvark compatible header for customer applications The I2 C bus is capable of connecting to a global I2 C bus on the board if JP10 is NOT set Table 5 9 Aardvark JP2 Header Pin Connections JP2 Pin Number Signal Name MachXO3 Ball Locati...

Page 21: ... receptacle which is compatible with the GPIO header of Raspberry Pi 2 3 serial models Table 5 10 Raspberry Pi JP3 Header Pin Connections JP3 Pin Number Signal Name MachXO3 Ball Location 1 3 3V_RASP 2 RASP_5V 3 RASP_IO02 T6 4 RASP_5V 5 RASP_IO03 V1 6 GND 7 RASP_IO04 U2 8 RASP_IO14 P4 9 GND 10 RASP_IO15 N5 11 RASP_IO17 N6 12 RASP_IO18 N7 13 RASP_IO27 P5 14 GND 15 RASP_IO22 P6 16 RASP_IO23 R3 17 3 3...

Page 22: ...lders The specifications and information herein are subject to change without notice 22 FPGA EB 02004 1 0 Table 5 10 Raspberry Pi JP3 Header Pin Connections continued JP3 Pin Number Signal Name MachXO3 Ball Location 38 RASP_IO20 Y2 39 GND 40 RASP_IO21 Y3 Notes 3 3 V power is supplied from Raspberry Pi board 5 V power can come from either the Raspberry Pi board or the MachXO3 9400 development board...

Page 23: ...O3 Bank0 ASC U7 MachXO3 Bank4 MachXO3 Bank1 MachXO3 Bank2 FX12 Headers U4 U5 Arduino Header J2 R87 R84 R85 R96 R37 R35 R44 R45 R81 R71 R70 R83 R97 R98 Figure 6 1 I2 C Topology The board provides two options for accessing the global I2 C bus from external cables One is from the mini USB cable J11 through FTDI U1 and the other is from the Aardvark header JP2 for an Aardvark cable Two analog MUXes as...

Page 24: ...A SDA0 R44 DNI 10 U18 AR_SCL SCL0 R45 DNI 2 FX12 headers U4 U5 39 AA11 SDA1 SDA0 R81 DNI 40 AB11 SCL1 SCL0 R83 DNI FX12 headers U4 U5 13 AB13 SDA2 SDA0 R71 DNI 14 AA13 SCL2 SCL0 R70 DNI 3 Raspberry Pi header JP3 3 T6 RASP_IO02 SDA0 R84 DNI 5 V1 RASP_IO03 SCL0 R96 DNI 27 V5 RASP_ID_SD SDA0 R87 DNI 28 T7 RASP_ID_SC SCL0 R85 DNI 4 ASC device U7 14 K2 I2C_SDA0 SDA0 R97 DI 15 K1 I2C_SCL0 SDA0 R98 DI No...

Page 25: ...6 4 By default the MachXO3 can boot up from SPI Flash with Master SPI mode Table 6 4 MachXO3 SPI Configuration Options Master SPI Device Reference Master CS Pin Number of Reference Part Slave SPI Device Reference Slave CS Pin Number of Reference Part MachXO3 U3 CSSPIN AA3 SPI Flash U6 CS 1 MachXO3 U3 CSSPIN AA3 FX12 U4 U5 FX_SN 10 Aardvark JP2 SS 9 MachXO3 U3 SN AB21 Arduino J2 AR_SS_IO10 3 MachXO...

Page 26: ...the four switches of SW1 as shown in the circuit design in Figure 7 1 The CTS side actuated DIP switches are connected to logic level 0 when in the ON position as shown in Figure 7 2 Figure 7 1 Four Position DIP Switch Circuits Figure 7 2 Four Position DIP Switch Photograph One side of each switch is connected to GPIOs within the VCCIO5 bank and pulled up through 4 7 kΩ resistors The other side is...

Page 27: ...are designed for general purpose applications and SW5 is designed with additional jumper JP5 as shown in Figure 7 3 SW5 can be used as PROGRMN push button when JP5 is set to trigger the configuration process without power cycle For detailed information on PROGRAMN refer to TN1279 MachXO3 Programming and Configuration Usage Guide Figure 7 3 Push Button SW5 Circuit Design 7 3 General Purpose LEDs Th...

Page 28: ... pairs of unused LVDS outputs pins that are connected to test points for possible customer applications The LVDS test points are detailed in Table 7 4 Table 7 4 LVDS Test Points Signal Name MachXO3 Ball Location Test Point Comments LVDS_OUT0_P B1 TP63 LVDS output pair 0 LVDS_OUT0_N A2 TP64 LVDS_OUT1_P B2 TP65 LVDS output pair 1 LVDS_OUT1_N A3 TP66 LVDS_OUT2_P B3 TP67 LVDS output pair 2 LVDS_OUT2_N...

Page 29: ...ective holders The specifications and information herein are subject to change without notice FPGA EB 02004 1 0 29 7 5 General Purpose DDR Outputs Graphics Double Data Rate GDDR signals are wired to the test pads for signal validation Table 7 5 GDDR Test Points Signal Name MachXO3 Ball Location Test Point GDDR_DQ0 R22 TP93 GDDR_DQ1 R21 TP94 GDDR_DQ2 T22 TP95 GDDR_DQ3 T21 TP96 GDDR_DQ4 Y22 TP97 GDD...

Page 30: ...ASC_ CLK L1 7 8 MHz clock output from ASC TP14 ASC_RESETb L3 43 ASC device reset Active Low TP13 ASC_WRCLK M1 6 ASC I F clock signal to ASC TP12 ASC_RDAT N1 5 ASC I F data signal from ASC TP11 ASC_WDAT P1 4 ASC I F data signal to ASC TP10 I2C_WRITE_PROTECT N2 44 I2C Configuration Write Control signal when WP 1 0 10 in ASC WRITEPROTECT_USERTAG Register pull high to enable overwriting by I2C instruc...

Page 31: ...nt Monitors IMONs is connected to monitor the MachXO3 core current using resistor R181 as a shunt The IMON uses the differential voltage across R181 to monitor the current The ASC has two IMONs one is used for lower voltage 0 3 V to 5 9 V current monitoring pins 19 and 20 and the other HIMON pins 17 and 18 is used for higher voltage 4 5 V to 13 2 V current monitoring Pin 18 is a shared input pin u...

Page 32: ...sors as listed in Table 8 4 One TMON is connected to a PNP transistor as shown in Figure 8 4 and the other TMON is connected to an NPN transistor as shown in Figure 8 5 Note that the noise suppression capacitors C33 and C34 are shown on the schematic as close to the transistors However they are physically close to the L ASC10 U7 Table 8 4 ASC TMON Connections Temperature Sensor Reference ASC Signa...

Page 33: ...D11 TP46 0 ASC_LED4 47 D12 TP47 0 ASC_LED5 48 D13 TP48 0 ASC_LED6 1 D14 TP49 0 ASC_LED8 11 D15 TP50 0 ASC_LED9 12 D16 TP51 0 ASC_LED10 13 D17 TP52 0 Caution The MachXO3 9400 Development Board contains ESD sensitive components ESD safe practices should be followed while handling and using the development board Note The LEDs are lined up in sequence as shown in Figure 8 6 8 6 ASC HVOUT and Trim Pins...

Page 34: ...evelopment Board Diamond 3 9 or higher Diamond Programmer 3 9 or higher LatticeMico System Development Tools Storage and Handling Static electricity can shorten the life span of electronic components Observe these tips to prevent damage that can occur from electrostatic discharge Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband Store the develop...

Page 35: ...ce FPGA EB 02004 1 0 35 References Lattice Semiconductor Documents Related documents available from your Lattice Semiconductor sales representative are listed on the table below Document Title DS1042 L ASC10 Data Sheet DS1047 MachXO3 Family Data Sheet FPGA UG 02021 LCMXO3LF 9400C Simple Hardware Management Demo User Guide FPGA UG 02022 LCMXO3LF 9400C Hitless I O Demo User Guide FPGA UG 02023 LCMXO...

Page 36: ...claimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 36 FPGA EB 02004 1 0 Technical Support Assistance Submit a technical support case through www latticesemi com techsupport ...

Page 37: ...0 05 Arduino Headers BANK1 06 CrossLink Headers BANK2 07 Raspberry Pi Header Others BANK3 4 5 08 Analog Sense and Control 09 Power Decoupling and LEDs 10 Power Regulators Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications http www latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 4 0 MachXO3 9400 Dev Brd A 1 10 Monday May 22 2017 B Title page Date Size Sche...

Page 38: ... B A A Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications http www latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 4 0 MachXO3 9400 Dev Brd B 2 10 Monday May 22 2017 B Block Diagram Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications http www latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 4 0 MachXO3 9400 Dev Brd...

Page 39: ...1uF R9 2 2K R12 10K R19 12K R22 0 DNI C103 10nF R25 0 C1 4 7uF 1 2 R2 4 7K L2 600ohm 500mA 1 2 R18 0 DNI R23 0 L1 600ohm 500mA 1 2 C5 10uF FTDI High Speed USB FT2232H FT2232HL U1 VREGIN 50 VREGOUT 49 DM 7 DP 8 REF 6 RESET 14 EECS 63 EECLK 62 EEDATA 61 OSCI 2 OSCO 3 TEST 13 ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19 VPHY 4 VPLL 9 VCORE 12 VCORE 37 VCORE 64 VCCIO 20 VCCIO 31 VCCIO 42 VCCIO 56 AGND 10 G...

Page 40: ...PT23C G11 PT23D F11 PT24A B11 PT24B A11 PT24C E11 PT24D D11 PT27A D12 PT27B E12 PT28C E13 PT28D F13 PT29A A13 PT29B B13 PT29C C13 PT29D D13 PT30A A14 PT30B B14 PT30C C14 PT30D D14 PT38A A15 PT38B B15 PT38C C15 PT38D D15 PT39A A16 PT39B B17 PT39C C17 PT39D D16 PT40A A17 PT40B B18 PT40C E16 PT40D D17 PT41C C18 PT41D D18 PT42A A19 PT42B B20 PT42C F15 PT42D G15 PT43C C19 PT43D C20 TP75 R267 10K R34 2K...

Page 41: ...O5 PWM 6 IO6 PWM 7 IO7 8 IO2 3 J10 SMA DNI 1 5 J4 Header 1x8 N A 1 IOREF 2 3V3 4 5V0 5 GND1 6 GND2 7 VIN 8 RESET 3 BANK 1 XO3L_10K_484CABGA U3G PR30B W20 PR30A V18 PR29D V19 PR29B Y21 PR29C U17 PR29A AA22 PR25B W22 PR25A V22 PR20B R21 PR20A R22 PR19B P21 PR19A N22 PR17B_PCLKC1_0 M21 PR17A_PCLKT1_0 M22 PR16B L21 PR16A K22 PR14B L16 PR14A L17 PR7B H21 PR7A H22 PR3B_R_GPLLC_IN D21 PR3A_R_GPLLT_IN D22...

Page 42: ...B43B AA19 PB44A AB20 PB44B AA20 PB46A_SN AB21 PB46B_SI SISPI AA21 PB35A AB15 PB35B AA15 PB11A AA6 PB11B AB6 PB11C W6 PB11D V7 PB13A AA7 PB13B AB7 PB16C V9 PB16D W8 PB18C Y8 PB18D W9 PB19A AA9 PB19B AB9 PB19C T10 PB19D U10 PB22C T11 PB22D U11 PB27A Y12 PB27B T12 PB27C U12 PB27D V12 PB29C V13 PB29D U13 PB30C Y13 PB30D W13 PB33C Y14 PB33D W14 PB32A T13 PB32B T14 PB32C U14 PB32D V14 PB35C Y15 PB35D W1...

Page 43: ... PL4D H6 PL5A D1 PL5B E2 PL5C E3 PL5D F4 PL13A L7 PL13B K5 PL13C K4 PL13D K3 PL14A K2 PL14B K1 PL16A_PCLKT4_0 L1 PL16B_PCLKC4_0 M2 PL20A P4 PL20B N5 PL20C N6 PL20D N7 PL21A R2 PL21B T1 PL21C P5 PL21D P6 PL26C T5 PL26D T6 PL14C L6 PL14D L5 PL16C L3 PL16D L4 PL6C G3 PL6D G4 PL6A E1 PL6B F1 PL25A T2 PL25B U1 PL24A R3 PL24B R4 PL24C R5 PL24D P7 PL25C R6 PL25D R7 PL26A T3 PL26B T4 PL17A M1 PL17B N1 PL1...

Page 44: ...9 HVOUT4 10 GPIO8 11 GPIO9 12 SDA 14 SCL 15 I2C_ADDR 16 HIMONP 17 HIMONN_HVMON 18 IMON1P 19 IMON1N 20 TMON1P 21 TMON1N 22 TMON2P 23 TMON2N 24 VMON1GS 25 VMON1 26 VMON2GS 27 VMON2 28 VMON3GS 29 VMON3 30 VMON4GS 31 VMON4 32 VCC 33 VMON5 34 VMON6 35 VMON7 36 VMON8 37 VMON9 38 TRIM1 39 TRIM2 40 TRIM3 41 TRIM4 42 RESETb 43 GPIO1 44 GPIO2 45 GPIO3 46 GPIO4 47 GPIO5 48 GPIO10 13 TP37 AB12 AD11 AG13 AE19 ...

Page 45: ...F C115 0 01uF C46 0 1uF C65 10uF D6 Red 1 2 C39 0 01uF C75 0 1uF R173 2 2k R116 1K R122 2 2k C69 0 01uF C79 0 1uF C74 0 01uF R174 2 2k D16 Red C53 0 01uF D10 Red R115 1K C67 0 01uF C48 0 01uF XO3L_10K_484CABGA U3F GND1 A1 GND2 A22 GND3 B7 GND4 B16 GND5 C2 GND6 C11 GND7 E5 GND8 E18 GND9 F2 GND10 F21 GND11 H8 GND12 H10 GND13 H13 GND14 H15 GND15 J9 GND16 J10 GND17 J11 GND18 J12 GND19 J13 GND20 J14 GN...

Page 46: ...eet Title Lattice Semiconductor Applications http www latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 4 0 MachXO3 9400 Dev Brd B 10 10 Monday May 22 2017 B Power Regulators Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications http www latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 4 0 MachXO3 9400 Dev Brd B 10 10 Monday May 22 2017 B Po...

Page 47: ...B13 AA13 AG14 AF14 AE14 AD14 AC14 AB14 AA14 AG15 AF15 AE15 AD15 AC15 AB15 AA15 AG16 AF16 AE16 AD16 AC16 AB16 AA16 AG17 AF17 AE17 AD17 AC17 AB17 AA17 AG18 AF18 AE18 AD18 AC18 AB18 AA18 AG19 AF19 AE19 AD19 AC19 AB19 AA19 AG20 AF20 AE20 AD20 AC20 AB20 AA20 AG21 AF21 AE21 AD21 AC21 AB21 AA21 77 T POINT R TP DNI 2 C1 C3 2 4 7uF C0603 CL10A475KA8NQNC Samsung CAP CER 4 7UF 6 3V 10 X5R 0603 3 C2 C4 C6 C7 ...

Page 48: ...0603 12 C36 C40 C46 C50 C56 C60 C66 C70 C75 C79 C83 C111 12 0 1uF C0201 CL03A104KA3NNNC Samsung CAP CER 0 1UF 16V 10 X5R 0201 13 C37 C38 C39 C41 C42 C43 C44 C47 C48 C49 C51 C52 C53 C54 C57 C58 C59 C61 C62 C63 C64 C67 C68 C69 C71 C72 C73 C74 C76 C77 C80 C81 C84 C85 C105 C106 C107 C108 C109 C110 C112 C114 C115 43 0 01uF C0201 CL03A103KA3NNNC Samsung CAP CER 10000PF 16V 10 X7R 0201 14 C89 C95 2 22uF ...

Page 49: ...CONN HEADER 8POS 100 VERT TIN DNI 24 J5 1 Header 1x6 CONF1X6 254P_1596X 240X850H_T H CONN HEADER 6POS 100 VERT TIN DNI 25 J10 1 SMA bnc5 100 280t 5 1814832 1 TE Connectivity CONN SMA JACK STR 50 OHM PCB DNI 26 J11 1 USB_MINI _B usb2 0 rec 240 0001 9 UX60 MB 5ST Hirose CONN RECEPT MINI USB2 0 5POS 27 J12 J13 2 GND TUR_TH 1573 2 Keystone Electronics Terminal Turret Connector Single End 0 186 4 72mm ...

Page 50: ... OHM 1 10W 1 0603 SMD 37 R4 R5 R6 R7 R23 R24 R25 R31 R72 R73 R99 R103 R136 R140 R269 R 270 16 0 R0603 RC0603FR 070RL Yageo RES 0 0 OHM 1 10W JUMP 0603 SMD 38 R8 R9 R121 R122 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 20 2 2k R0603 RC0603FR 072K2L Yageo 39 R10 R19 2 12K R0603 RC0603FR 0712KL Yageo RES 12K OHM 1 10W 1 0603 SMD 40 R11 R12 R13 R65 R66 R69 R80 R102 ...

Page 51: ...603 RC0603FR 071KL Yageo RES 1K OHM 1 10W 1 0603 SMD 49 R97 R98 R160 3 0 R0603 RC0603FR 070RL Yageo Res 1 10W 0 0 Ohm 5 0603 50 R100 R101 2 22 R0603 RC0603FR 0722RL Yageo 51 R104 R105 R106 R107 R108 R182 6 270 R0603 RC0603FR 07270RL Yageo 52 R109 R110 R111 R112 4 100 R0603 RC0603FR 07100RL Yageo 53 R123 R124 R125 R126 R132 R133 R134 7 1 R0603 RC0603FR 071RL Yageo RES 1 0 OHM 25W 5 0603 SMD 54 R127...

Page 52: ...P2 TP53 TP54 TP55 TP56 TP57 TP58 TP59 TP60 TP61 TP62 TP81 TP82 TP83 TP84 TP85 17 TP_S_40_ 63 TP Square test point 40mil inner diameter 63mil outer diameter DNI 66 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 TP42 TP43 TP44 TP45 TP46 TP47 TP48 TP49 TP50 TP51 TP52 TP63 TP64 TP65 TP66 TP...

Page 53: ...Hirose FX12 FX12B 40P 0 4SV Hirose CONN PLUG 40POS 0 4MM SMD SHIELD DNI 73 U6 1 S25FL116 K0XMFI04 3 so8_50_ 244 S25FL116K0XMFI04 3 Cypress IC FLASH 16MBIT 108MHZ 8SOIC 74 U7 1 ASC10 SG48 TQFN_48 L ASC10 1SG48I Lattice ASC Device 75 U8 1 NCP1117 sot223_4p NCP1117ST33T3G ON semi IC REG LDO 3 3V 1A SOT223 76 U9 1 sot223_4p IC REG LDO SOT223 3 DNI 77 U10 U11 2 FSA4157_ Analog_ Sw SOP 6 26 FSA4157P6X F...

Page 54: ...eir respective holders The specifications and information herein are subject to change without notice 54 FPGA EB 02004 1 0 Appendix C Predefined Preference File Listing These names are generated by the Platform Designer tool in Diamond software and can be copied into the preference file or entered into the Spreadsheet view ASC0 Connections LOCATE COMP ASC0_RSTN SITE L3 LOCATE COMP ASC0_CLK SITE L1...

Page 55: ...ITE G4 LOCATE COMP XLED6 SITE G3 LOCATE COMP XLED0 SITE D1 LOCATE COMP XLED1 SITE E2 LOCATE COMP XLED4 SITE E1 LOCATE COMP XLED2 SITE E3 LOCATE COMP XLED5 SITE F1 XO3 DIP Switch Connections LOCATE COMP DIP_SW1 SITE H5 LOCATE COMP DIP_SW2 SITE J5 LOCATE COMP DIP_SW3 SITE J4 LOCATE COMP DIP_SW4 SITE J3 XO3 Push Button Switch Connections LOCATE COMP PB1 SITE D3 LOCATE COMP PB2 SITE D4 LOCATE COMP PB3...

Page 56: ...LOCATE COMP RASP_IO03 SITE V1 LOCATE COMP RASP_IO04 SITE U2 LOCATE COMP RASP_IO05 SITE U3 LOCATE COMP RASP_IO06 SITE U4 LOCATE COMP RASP_IO07 SITE T5 LOCATE COMP RASP_IO08 SITE T4 LOCATE COMP RASP_IO09 SITE R7 LOCATE COMP RASP_IO10 SITE R6 LOCATE COMP RASP_IO11 SITE T3 LOCATE COMP RASP_IO12 SITE V4 LOCATE COMP RASP_IO13 SITE U5 LOCATE COMP RASP_IO14 SITE P4 LOCATE COMP RASP_IO15 SITE N5 LOCATE COM...

Page 57: ...CATE COMP EXPCON_IO29 SITE E12 LOCATE COMP EXPCON_IO30 SITE D14 LOCATE COMP EXPCON_IO31 SITE C15 LOCATE COMP EXPCON_IO32 SITE C17 LOCATE COMP EXPCON_IO33 SITE D15 LOCATE COMP EXPCON_IO34 SITE C18 LOCATE COMP EXPCON_IO35 SITE D16 LOCATE COMP EXPCON_IO36 SITE C19 LOCATE COMP EXPCON_IO37 SITE D17 LOCATE COMP EXPCON_IO38 SITE D18 LOCATE COMP EXPCON_IO39 SITE C20 LOCATE COMP EXPCON_IO40 SITE E16 LOCATE...

Page 58: ..._N SITE AB10 LOCATE COMP CH0_DATA0_P SITE AA4 LOCATE COMP CH0_DATA0_N SITE AB4 LOCATE COMP CH0_DATA1_P SITE AA2 LOCATE COMP CH0_DATA1_N SITE AB2 LOCATE COMP CH0_DATA2_P SITE AA5 LOCATE COMP CH0_DATA2_N SITE AB5 LOCATE COMP CH0_DATA3_P SITE AA8 LOCATE COMP CH0_DATA3_N SITE AB8 LOCATE COMP CH1_DCK_P SITE AB12 LOCATE COMP CH1_DCK_N SITE AA12 LOCATE COMP CH1_DATA0_P SITE AB16 LOCATE COMP CH1_DATA0_N S...

Page 59: ...emi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02004 1 0 59 XO3 CrossLink Connections Continued LOCATE COMP FX_SN SITE AA3 LOCATE COMP FX_SCLK SITE T9 LOCATE COMP FX_MOSI SITE AA21 LOCATE COMP FX_MISO SITE U9 LOCATE COMP RESETN SITE AB3 ...

Page 60: ...tents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 60 FPGA EB 02004 1 0 Revision History Date Version Change Summary May 2017 1 0 Initial release ...

Page 61: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com ...

Page 62: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LCMXO3LF 9400C ASC B EVN ...

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