MachXO3-9400 Development Board
Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-EB-02004-1.0
5.3.
FX12 Headers (DNI)
The board provides two headers – U4 and U5 to connect to FX12 compatible boards or cables. Each header has eight
pairs of Low-Voltage Differential Signaling (LVDS) signals for high speed data receiver.
Table 5.7. FX12 U4 Header Pin Connections
U4 Pin Number
Signal Name
MachXO3 Ball Location
1
CH0_DCK_P
AA10
2
CH0_DCK_N
AB10
3
GND
—
4
CH0_DATA0_P
AA4
5
CH0_DATA0_N
AB4
6
GND
—
7
CH0_DATA2_P
AA5
8
CH0_DATA2_N
AB5
9
GND
—
10
FX_SN*
—
11
FX_SCLK*
—
12
PWR_12V**
—
13
SDA2
AB13
14
SCL2
AA13
15
GND
—
16
CH2_DATA0_P
AA6
17
CH2_DATA0_N
AB6
18
GND
—
19
CH2_DCK_P
AA7
20
CH2_DCK_N
AB7
21
PWR_12V**
—
22
RESETN
AB3
23
PWR_5-0V*
—
24
CH0_DATA1_P
AA2
25
CH0_DATA1_N
AB2
26
PWR_3-3V*
—
27
CH0_DATA3_P
AA8
28
CH0_DATA3_N
AB8
29
PWR_1-8V*
—
30
FX_MOSI*
—
31
FX_MISO*
—
32
PWR_1-8V*
—
33
GND
—
34
GND
—
35
PWR_3-3V*
—
36
CH2_DATA1_P
AA9
37
CH2_DATA1_N
AB9