Lattice Semiconductor
Application Support
IPUG39_02.9, December 2010
28
10 Gb+ Ethernet MAC IP Core User’s Guide
Transmit Control (TX_CTL)
This register should be overwritten only when the TX MAC is disabled. Writing this register while the TX MAC is
active results in unpredictable behavior.
Table 5-4. Transmit Configuration Register Description
Receive Control (RX_CTL)
This register should be overwritten only when the RX MAC is disabled. Writing this register while the RX MAC is
active results in unpredictable behavior.
Table 5-5. Receive Control Register Description
Name: TX_CTL
Address: A02H
Bits
Name
Type
Default
Description
7:4
UNUSED
—
—
Reserved
3
Transmit_short
R/W
0
Transmit Short. When high, enables the Tx MAC to transmit
frames shorter than 64 bytes.
2
Tx_ifg_stretch
R/W
0
IFG Stretch Mode. When set, the Tx MAC operates in the IFG
stretch mode, to match the data rates of OC-192. The IPG
required to match OC192 is added to the value specified in
IPG_VAL.
1
FC_en
R/W
0
Flow-control Enable. When set, this enables the flow control
functionality of the Tx MAC. This bit should be set for the Tx
MAC to transmit a PAUSE frame.
0
Tx_pass_fcs
R/W
0
Transmit Pass FCS. When set, the FCS field generation is dis-
abled in the Tx MAC, and the user is responsible to generate
the appropriate FCS field.
Name: RX_CTL
Address: A03H
Bits
Name
Type
Default
Description
7
UNUSED
Reserved
6
drop_mac_ctrl
R/W
0
Drop MAC Control Frames. When set, all MAC control frames are
not passed on to the client interface.
5
receive_short
R/W
0
Receive Short Frames. When high, enables the Rx MAC to
receive frames shorter than 64 bytes.
4
receive_bc
R/W
0
Receive Broadcast. When high, enables the Rx MAC to receive
broadcast frames
3
receive_all_mc
R/W
0
Receive Multicast. When high, the multicast frames will be
received per the filtering rules for such frames. When low, no Mul-
ticast (except PAUSE) frames will be received.
2
rx_pause_en
R/W
0
Receive PAUSE. When set, the Rx MAC will indicate the PAUSE
frame reception to the Tx MAC. PAUSE frames are received and
transferred to the FIFO only when drop_mac_ctrl bit is NOT set.
1
rx_pass_fcs
R/W
0
Rx Pass FCS and Pad. When set, the FCS and any of the padding
bytes are passed to the FIFO. When low, the MAC will strip off the
FCS and any padding bytes before transferring it to the FIFO.
0
prms
R/W
0
Promiscuous Mode. When asserted, all filtering schemes are
abandoned and the Rx MAC receives frames with any address.
