Lattice Semiconductor
Functional Description
IPUG39_02.9, December 2010
11
10 Gb+ Ethernet MAC IP Core User’s Guide
Signal Descriptions
Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals
Port Name
Active State
I/O Type
Description
reset_n
Low
Input
Asynchronous reset signal – Resets the entire core when asserted.
tx_paustim[15:0]
N/A
Input
Contains parameters to be transmitted in a pause frame. Valid when
tx_pausreq is asserted.
tx_pausreq
Positive Edge
Input
Asserted to initiate the transmitting of a pause frame.
tx_is_paused
High
Output
Active when the transmitter has been placed in the pause state by a
received pause frame.
tx_data_avail
High
Input
Asserted to alert the MAC transmitter that the transmit FIFO has data ready
for transmission.
tx_read
High
Output
Transmit FIFO read request, asserted by the MAC transmitter in response
to signal tx_data_avail.
tx_data[63:0]
N/A
Input
Data read from transmit FIFO. The least significant byte (bits 7:0) is sent
out on the link first.
tx_byten[2:0]
N/A
Input
Indicates the valid bytes on the tx_data bus. Must be 7 except when tx_eof
is active.
0 - tx_data[7:0] valid
1 - tx_data[15:0] valid
2 - tx_data[23:0] valid
3 - tx_data[31:0] valid
4 - tx_data[39:0] valid
5 - tx_data[47:0] valid
6 - tx_data[55:0] valid
7 - tx_data[63:0] valid
tx_eof
High
Input
End of frame signal asserted with the last segment of the frame.
tx_force_err
High
Input
Indicates that the current frame has errors. This input is qualified with input
signal tx_eof.
tx_empty
High
Input
When asserted, indicates that the transmit FIFO is empty.
tx_statvec[25:0]
N/A
Output
Contains information on the frame transmitted (details given in the Func-
tional Description section of this document). This bus is qualified by the
tx_staten signal.
tx_staten
High
Output
When asserted, indicates that the contents of the tx_statvec bus are valid.
This signal is asserted for 3 txmac_clk periods.
rx_statvec[27:0]
N/A
Output
Contains information on the frame received (details given in the Functional
Description section of this document). This bus is qualified by the rx_staten
signal.
rx_staten
High
Output
When asserted, indicates that the contents of the rx_statvec bus are valid.
This signal is asserted for 3 rxmac_clk periods.
ignore_pkt
High
Input
Asserted to prevent a receive FIFO full condition. The Receive MAC will
continue dropping packets as long as this signal is asserted.
rx_write
High
Output
Driven by the MAC core to request a receive FIFO write.
rx_data[63:0]
N/A
Output
Contains data that is to be written into the receive FIFO.
rx_byten[2:0]
N/A
Output
Indicates the valid bytes on the rx_data bus. Must be 7 except when rx_eof
is active.
0 - rx_data[7:0] valid
1 - rx_data[15:0] valid
2 - rx_data[23:0] valid
3 - rx_data[31:0] valid
4 - rx_data[39:0] valid
5 - rx_data[47:0] valid
6 - rx_data[55:0] valid
7 - rx_data[63:0] valid
rx_sof
High
Output
Start of frame signal asserted with the first segment of the frame.
