Lattice Semiconductor
Parameter Settings
IPUG39_02.9, December 2010
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10 Gb+ Ethernet MAC IP Core User’s Guide
Evaluation Generation Options
PHY Interface
The reconciliation sublayer interface is implemented as a 64 bit wide single edge data bus and an 8-bit wide single
edge control bus. To allow this interface to conform to the XGMII definition DDR I/O cells are added at the top level
of the FPGA when this core is implemented. To allow this interface to conform to the XAUI definition, a
PCS/SERDES quad is added at the top level of the FPGA when this core is implemented. The top level file pro-
vided with this core contains the logic to implement one of these choices.
Clock Constraints
This parameter is used to specify whether timing constraints supporting either 10 Gbps or 12 Gbps data throughput
are included in the evaluation package provided with the IP core.
Management Statistics
This parameter determines whether the optional Statistics Counters will be included in the reference design.
Bits in Counters[13-40]
This parameter determines the width of the optional Statistics Counters.
