LanParty X58-T3EH6, User Manual

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BIOS Setup
DRAM Timing
Move the cursor to this field and press <Enter>. The following
screen will appear.
Memory Control Setting
Memory LowGap
DRAM Command Rate
CAS Latency Time (tCL)
RAS# to CAS# Delay (tRCD)
RAS# Precharge (tRP)
Precharge Delay (tRAS)
REF to ACT Delay (tRFC)
Write to PRE Delay(tWR)
Rank Write to Read (tWTR)
ACT to ACT Delay (tRRD)
Row Cycle Time (tRC)
Read CAS# Precharge(tRTP)
Four ACT WIN Time(tFAW)
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Timing
Item Help
Menu Level
XX
↑↓→←
: Move Enter: Select F1: General Help +/-/PU/PD: Value F10: Save ESC: Exit
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Auto
1536M
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
The settings on the screen are for reference only. Your version may not be
identical to this one.
Memory Control Setting
The options are Auto, Independent, Mirror, Lock and Spare.
Memory LowGap
The options are 1024M to 3072M.
DRAM Command Rate
The options are Auto, 1N, 2N and 3N.
CAS Latency Time (tCL)
This field is used to select the clock cycle of the CAS latency time.
The option selected specifies the timing delay before SDRAM starts
a read command after receiving it.