Command:
Byte
0
Checksum8
1
0xF8
2
0x00
3
0x09
4
Checksum16 (LSB)
5
Checksum16 (MSB)
Response:
Byte
0
Checksum8
1
0xF8
2
0x05
3
0x09
4
Checksum16 (LSB)
5
Checksum16 (MSB)
6
Errorcode
7
WatchdogOptions
8-9
TimeoutPeriod
10
DIOConfigA
11
DIOConfigB
12-13
DAC0
14-15
DAC1
5.3.13.3 - Extended WatchdogConfig
Controls a firmware based watchdog timer. Unattended systems requiring maximum up-time might use this capability to reset the
UE9 or the entire system. When any of the options are enabled, an internal timer is enabled which resets on any incoming Control
communication. If this timer reaches the defined TimeoutPeriod before being reset, the specified actions will occur. Note that while
streaming, data is only going out of the Control processor, so some other Control command will have to be called periodically to
reset the watchdog timer.
If the watchdog is accidentally configured to reset the processors with a very low timeout period (such as 1 second), it could be
difficult to establish any communication with the device. In such a case, the reset-to-default jumper can be used to turn off the
watchdog (sets bytes 7-10 to 0). Power up the UE9 with a short from FIO2<=>SCL, then remove the jumper and power cycle the
device again. This also returns Comm (Section 5.2.1) and Control (Section 5.3.2) settings to factory defaults.
The watchdog settings (bytes 7-10) are stored in non-volatile flash memory, so every call to this function where settings are
changed causes a flash erase/write. The Control flash has a rated endurance of at least 20000 writes, which is plenty for
reasonable operation, but if this function is called in a high-speed loop the flash could be damaged.
New features in the extended version:
Initial roll time: When the UE9 resets a longer timeout will be used. Once the watchdog has been reset the normal roll time
will be used.
Strict: Allow a specific key to be specified, so that only calling the WDT_Clear function with the matching key will reset the
WatchDog.
Command:
Byte
0
Csum8
1
0xF8
2
0x0D
3
0x09
4
C16L
5
C16H
6
Write Mask
7
SWDT settings
Bit 7: Reserved (0)
Bit 6: Reset Comm on Timeout
Bit 5: Reset Control on Timeout
Bit 4: Update Digital I/O B on Timeout
Bit 3: Update Digital I/O A on Timeout
Bit 2: Enable Strict Mode
Bit 1: Update DAC1 on Timeout
Bit 0: Update DAC0 on Timeout
8-9
TimeoutPeriod
10
DIO Response A
Bit 7: State
Bit 4-0: Digital IO #
11
DIO Response B
Bit 7: State
Bit 4-0: Digital IO #
68
Summary of Contents for UE9
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