DR600 Service Manual
152
FPGA
1PPS
R139
NC
R129
10K
DATE : APRIL 2010
PAGE : 7 of 8
VERSION : 1.0
EP4CE30F484
K1
D1
A8
B8
B7
A5
F10
C6
B4
F8
A3
B3
C4
C7
C8
B6
IO_B1___K1/__DATA0
IO_B1___D1/__DIFFIO_L8N/__DATA1_ASDO
IO_B8___A8/__DIFFIO_T20N/__DATA2/__DQ5T
IO_B8___B8/__DIFFIO_T20P/__DATA3/__DQ5T
IO_B8___B7/__DIFFIO_T19P/__DATA4/__DQ5T
IO_B8___A5/__DIFFIO_T11P/__DATA5/__DQ3T
IO_B8___F10/__DIFFIO_T8P/__DATA6/__DQ3T
IO_B8___C6/__DIFFIO_T7N/__DATA7/__DQ3T
IO_B8___B4/__DIFFIO_T6P/__DATA8/__DQ3T
IO_B8___F8/__DIFFIO_T5N/__DATA9/__DQ3T
IO_B8___A3/__DIFFIO_T4N/__DATA10/__DQ3T
IO_B8___B3/__DIFFIO_T4P/__DATA11/__DQ3T
IO_B8___C4/__DIFFIO_T3P/__DATA12/__DQS1T
IO_B8___C7/__DIFFIO_T16P/__DATA13/__DM5T
IO_B8___C8/__DIFFIO_T16N/__DATA14/__DQS3
IO_B8___B6/__DIFFIO_T18P/__DATA15/__DQ5T
K21
L21
N21
N22
E2
L22
F20
K22
E21
E4
E22
IO_B6___K21/__DIFFIO_R24P/__CLKUSR
IO_B6___L21/__DIFFIO_R27P/__CRC_ERROR
IO_B5___N21/__DIFFIO_R32P/__DEV_CLRN
IO_B5___N22/__DIFFIO_R32N/__DEV_OE
IO_B1___E2/__DIFFIO_L10P/__FLASH_NCE_NCS
IO_B6___L22/__DIFFIO_R27N/__INIT_DONE
IO_B6___F20/__DIFFIO_R8N/__NAVD/__DQ2R
IO_B6___K22/__DIFFIO_R24N/__NCEO
IO_B6___E21/__DIFFIO_R12P/__NOE
IO_B1___E4/__DIFFIO_L4P/__NRESET/__DQ2L
IO_B6___E22/__DIFFIO_R12N/__NWE/__DQ0R
B18
A17
B17
E14
F13
A15
B15
C13
D13
A14
B14
A13
B13
E11
F11
B10
A9
B9
A7
A6
C20
B21
B22
G18
IO_B7___B18/__DIFFIO_T45P/__PADD0
IO_B7___A17/__DIFFIO_T41N/__PADD1/__DQ2T
IO_B7___B17/__DIFFIO_T41P/__PADD2
IO_B7___E14/__DIFFIO_T38N/__PADD3/__DQ4T
IO_B7___F13/__DIFFIO_T37P/__PADD4/__DQS2
IO_B7___A15/__DIFFIO_T36N/__PADD5/__DQ4T
IO_B7___B15/__DIFFIO_T36P/__PADD6/__DQ4T
IO_B7___C13/__DIFFIO_T35N/__PADD7
IO_B7___D13/__DIFFIO_T35P/__PADD8/__DQ4T
IO_B7___A14/__DIFFIO_T31N/__PADD9/__DQ4T
IO_B7___B14/__DIFFIO_T31P/__PADD10/__DQ4
IO_B7___A13/__DIFFIO_T29N/__PADD11/__DQ4
IO_B7___B13/__DIFFIO_T29P/__PADD12/__DQS
IO_B7___E11/__DIFFIO_T27N/__PADD13
IO_B7___F11/__DIFFIO_T27P/__PADD14/__DM4
IO_B8___B10/__DIFFIO_T25P/__PADD15
IO_B8___A9/__DIFFIO_T24N/__PADD16/__DQ5T
IO_B8___B9/__DIFFIO_T24P/__PADD17/__DQS5
IO_B8___A7/__DIFFIO_T19N/__PADD18/__DQ5T
IO_B8___A6/__DIFFIO_T18N/__PADD19/__DQ5T
IO_B6___C20/__DIFFIO_R4N/__PADD20/__DQS2
IO_B6___B21/__DIFFIO_R5P/__PADD21/__DQ2R
IO_B6___B22/__DIFFIO_R5N/__PADD22/__DQ2R
IO_B6___G18/__DIFFIO_R7N/__PADD23/__DQ2R
CONF_DONE
M18
DCLK
K2
MSEL0
M17
MSEL1
L18
MSEL2
L17
MSEL3
K20
NCE
L3
NCONFIG
K5
NSTATUS
K6
TCK
L2
TDI
L5
TDO
L4
TMS
L1
U14-G
R140
4.7K
R137
1K
DATE : APRIL 2010
PAGE : 6 of 8
VERSION : 1.0
EP4CE30F484
G5
VREFB1N0
H7
VREFB1N1
H5
VREFB1N2
J3
VREFB1N3
M5
VREFB2N0
P5
VREFB2N1
T3
VREFB2N2
R5
VREFB2N3
Y4
VREFB3N3
AB4
VREFB3N2
V9
VREFB3N1
U11
VREFB3N0
V12
VREFB4N3
W14
VREFB4N2
AA18
VREFB4N1
V16
VREFB4N0
W19
VREFB5N3
R17
VREFB5N2
P20
VREFB5N1
M16
VREFB5N0
K19
VREFB6N3
J18
VREFB6N2
H18
VREFB6N1
D20
VREFB6N0
D17
VREFB7N0
D15
VREFB7N1
C15
VREFB7N2
E13
VREFB7N3
C10
VREFB8N0
E9
VREFB8N1
B5
VREFB8N2
D6
VREFB8N3
G1
A11
B11
AB12
AA12
AB11
AA11
T2
T1
G21
G22
T21
T22
A12
B12
CLK1___G1/__DIFFCLK_0N
CLK10___A11/__DIFFCLK_4N
CLK11___B11/__DIFFCLK_4P
CLK12___AB12/__DIFFCLK_7N
CLK13___AA12/__DIFFCLK_7P
CLK14___AB11/__DIFFCLK_6N
CLK15___AA11/__DIFFCLK_6P
CLK2___T2/__DIFFCLK_1P
CLK3___T1/__DIFFCLK_1N
CLK4___G21/__DIFFCLK_2P
CLK5___G22/__DIFFCLK_2N
CLK6___T21/__DIFFCLK_3P
CLK7___T22/__DIFFCLK_3N
CLK8___A12/__DIFFCLK_5N
CLK9___B12/__DIFFCLK_5P
U14-F
R135
33
1
RF
GND
2
GND
3
GND
4
GND
5
J6
SMA
OE
OUT
VSS
VDD
4
1
3
2
Y5
12.8MHz
R332
0
C304
0.1uF
R181
NC
VOUT
1
2
V-
3
+IN
4
-IN
V+
5
U38
AD8031
TP4
C170
0.1uF
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
J5
CON10
R128
10K
R180
100R
R123
33
R185
NC
R134
4.7K
R141
NC
R136
33
R127
33
R138
4.7K
C296
33
R124
10K
R131
10K
R184
NC
R132
10K
1
RF
GND
2
GND
3
GND
4
GND
5
J7
SMA
R130
10K
C299
0.1uF
C136
0.1uF
R133
4.7K
R362
33
R126
33
R125
10K
C112
1uF/25V
C137
1uF/25V
+
C218
4.7uF/6.3V
+
C228
4.7uF/6.3V
R95
17R
L20
680nH
L21
470nH
L22
180nH
L23
470nH
L24
220nH
L25
270nH
L26
180nH
R107
0R
2 1
VSS
3
CE
VIN
4
NCVOUT
5
U20
XC6209F302PR
+
C243
10uF/16V
R28
17R
R29
17R
R94
0
+
C369
10uF/16V
12M8_FPGA
+
C242
10uF/16V
C371
100P
C372
33P
C373
470P
C429
0.1uF
C301
82pF
C303
82pF
C309
100pF
C308
120pF
C307
82pF
C306
33pF
C305
150pF
VCCIO
VCCA
VCCA
3V_TCXO_12M8
VCCIO
3V_TCXO_12M8
FPGA_CONF_DONE
FPGA_NSTATUS
FPGA_NCONFIG
FPGA_DCLK
FPGA_DATA0
AD9864_CLK1
EMA_OE#
EMA_WE#
FPGA_CS#
NAND_R/B
EMA_WAIT1
EMA_DQM0
SYNCB
EMA_DQM1
EMA_BA0
AD9864_DATAOUTA1
AD9864_FS1
EMA_BA1
FPGA_INT0
FPGA_INT1
FPGA_INT2
FPGA_INT3
TCXO_EN_DAC
1PPS
EMA_D8
EMA_D15
EMA_D14
EMA_D13
EMA_A5
EMA_A3
EMA_D3
EMA_A2
EMA_D2
EMA_A1
EMA_D1
EMA_A0
EMA_D0
EMA_D7
EMA_D5
EMA_A10
EMA_A9
EMA_D6
EMA_A8
EMA_A7
EMA_D4
EMA_A6
EMA_D12
EMA_D11
EMA_A4
EMA_D10
EMA_D9
3V_TCXO_12M8
8V
12M8HZ_OSC
12M8HZ_INT
12M8HZ_OSC
12M8HZ_INT
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
FPGA_TCK
FPGA_TDO
FPGA_TMS
FPGA_TDI
Summary of Contents for DR600
Page 1: ......
Page 37: ...DR600 Service Manual 33 ...
Page 110: ...DR600 Service Manual Figure 2 Rx Module Bottom Board PCB View 106 ...
Page 111: ...DR600 Service Manual Figure 3 Tx Module Top Board PCB View 107 ...
Page 113: ...DR600 Service Manual Figure 6 Baseband Mainboard Top Board PCB View 109 ...
Page 114: ...DR600 Service Manual Figure 7 Baseband Mainboard Bottom Board PCB View 110 ...
Page 116: ...DR600 Service Manual Figure 10 Power Board Top Board PCB View 112 ...
Page 118: ...DR600 Service Manual Figure 13 Enternet Board Top Board PCB View 114 ...
Page 119: ...DR600 Service Manual Figure 14 Enternet Board Bop Board PCB View 115 ...
Page 150: ...DR600 Service Manual Figure 21 Baseband Mainboard Schematic Diagram 146 ...