Figure
43
Refer to
“System Block Diagram” on page
for in-depth RF path information
Address and Data Example 1 (Port 5 and 14)
Table 1
2
N5242A/B Test Port and Data Values
Address
Source Path
Receiver Path
Data
1
2
4
8
16
32
64
128
0
Ports
1
5
9
13
1
5
9
13
16
Ports
3
6
10
14
3
6
10
14
32
Ports
4
7
11
15
4
7
11
15
64
Ports
2
8
12
16
2
8
12
16
Port 3
(2)
C
A
RCVR
C
IN
Port 1
CPLR
THRU
SOURCE
OUT
RCVR
A
IN
CPLR
ARM
Keysight 4-Port
PNA
NOTE:
PNA & PNA-X Port orientation is shown. PNA-L RF interconnections are the same.
( PNA-L )
CPLR
THRU
SOURCE
OUT
CPLR
ARM
Port 6
Port 9
Port 10
Port 13
SOURCE SIGNAL
RCVR SIGNAL
S200
S201
1
2
3
4
C
1
2
3
4
C
S100
S101
1
2
3
4
C
1
2
3
4
C
DUT
Receiver Port
Source Port
Port 5
Port 14
0.2
16.128
U3042AE12 User's and Service Guide
53
