Kenwood TS-2000, Service Manual

Page: 50 / 171

50
TS-2000/X
DDS : AD9851BRS (TX-RX 3 unit IC4)
■
Block diagram
6 x REFCLK
Multiplier
High
Speed
DDS
10-bit
DAC
32-bit
Tuning
Word
Phase
and
Control
Words
Frequency/Phase
Data Register
Data Input Register
Parallel
Load
Ref
Clock in
Master
Reset
Frequency
Update/Data
Register
Reset
Word Load
Clock
Serial
Load
DAC R
SET
Analog
out
Analog
in
Clock out
Clock out
Comparator
+
–
GND
+Vs
1 bit x
40 Loads
8 bits x
5 Loads
Frequency, Phase
and Control Data Input
■
Pin function
No. Name Function
1~4 D3~D0 8-bit data input. The data port for loading
25~28 D7~D4 the 32-bit frequency and 8-bit phase/control
words. D7 = MSB, D0 = LSB. D7, pin 25,
also serves as the input pin 40-bit serial data
word.
5 PGND 6 x REFCLK multiplier ground connection.
6 PVCC 6 x REFCLK multiplier positive supply
voltage pin.
7 W CLK Word load clock. Rising edge loads the
parallel or serial frequency/phase/control
words asynchronously into the 40-bit input
register.
8 FQ UD Frequency update. Arising edge asynchro-
nously transfers the contents of the 40-bit
input register to be acted upon by the DDS
core. FQ UD should be issued when the
contents of the input register are known to
contain only valid, allowable data.
9 REFCLOCK Reference clock input. CMOS/TTL level
pulse train, direct or via the 6 x REFCLK
multiplier. In direct mode, this is also the
SYSTEM CLOCK. If the 6 x REFCLK multi-
plier is engaged, then the output of the
multiplier is the SYSTEM CLOCK. The rising
edge of the SYSTEM CLOCK initiates
operations.
No. Name Function
10,19 AGND Analog ground. The ground return for the
analog circuitry (DAC and comparator).
11,18 AVDD Positive supply voltage for analog circuitry
(DAC and comparator, pin 18) and bandgap
voltage reference (pin 11).
12 RSET The DAC’s external RSET connection–
nominally a 3.92k
Ω
resistor to ground for
10mA out. This sets the DAC full-scale
output current available from IOUT and
IOUTB. RSET = 39.93/IOUT.
13 VOUTN Voltage output negative. The comparator’s
“complementary” CMOS logic level output.
14 VOUTP Voltage output positive. The comparator’s
“true” CMOS logic level output.
15 VINN Voltage input negative. The comparator’s
inverting input.
16 VINP Voltage input positive. The comparator’s
noninverting input.
17 DACBP DAC bypass connection. This is he DAC
voltage reference bypass connection
normally NC (no connect) for optimum
SFDR performance.
20 IOUTB The “complementary” DAC output with
same characteristics as IOUT except that
IOUTB = (full-scale output – IOUT). Output
load should equal that of IOUT for best
SFDR performance.
21 IOUT The “true” output of the balanced DAC.
Current is “sourcing” and requires current
to voltage conversion, usually a resistor or
transformer referenced to GND.
IOUT = (full-scale output – IOUTB).
22 RESET Master reset pin, active high, clears DDS
accumulator and phase offset register to
achieve 0Hz and 0
°
output phase.
Sets programming to parallel mode and
disengages the 6 x REFCLK multiplier.
Reset does mot clear the 40-bit input
register. On power up, asserting RESET
should be the first priority before program-
ming commences.
23 DVDD Positive supply voltage pin for digital circuitry.
24 DGND Digital ground. The ground return pin for the
digital circuitry.
SEMICONDUCTOR DATA