43
TS-2000/X
DSP : 320VC5402PGE (Control unit IC515,516)
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Pin description
Pin name Type*
Description
Data signal
A19~A0
O/Z
Parallel address bus A19 (MSB) to A0 (LSB). The low-order 16 bits (A0 to A15) of the address pin are multiplexed to
address to external memory (data, program) or I/O. The high-order 4 bits (A16 to A19) are used to address to external
program space. These pins are high impedance when in hold mode or when OFF is low.
D15~D0
I/O/Z
Parallel data bus D15 (MSB) to D0 (LSB). D15 to D0 are multiplexed to transfer data between the core CPU and
external data/program memory or I/O device. The data bus becomes high impedance when data is not output or
RS or HOLD is low. It also becomes high impedance when OFF is low.
The data bus has a bus holder to reduce power consumption of unused pins. When there is a bus holder, external
bias resistors for unused pins are not necessary. When '5402 does not drive the data bus, the bus holder retains the
preceding logic level pin. The '5402 data bus holder is disabled on reset, and enabled/disabled through the BH bit of
the bank switching control register (BSCR).
Initialization, interrupt and reset operation
IACK
O/Z
Interrupt signal. Interrupt reception and interrupt vector specified by A15 to A0 are fetched by the program counter.
It becomes high impedance when OFF is low.
INT0~
I
External user interrupt input. INT0 to INT3 have priorities and can be masked by interrupt mask resister (IMR) and
INT3
interrupt mode bit. Polling and reset can be performed by the interrupt flag register (IFR).
NMI
I
Interrupt signal that cannot be masked. This external interrupt cannot be masked by INTM or IMR.
When NMI is low, the vector is trapped.
RS
I
Reset. RS stops DSP operation and initializes the CPU and peripheral. When RS goes high, execution starts from
0FF80h address of the program memory. RS affects various registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode selection. If it is low on reset, the microcomputer mode is selected, and the
internal program ROM is mapped to the high-order 4K words of the program memory space. If it is high on reset, the
microprocessor mode is selected and the onchip ROM is erased from the program space. This pin is sampled only on
reset, and when the MP/MC bit of the processor mode status (PMST) register is reset, the selected mode is made invalid.
Multi-processing signal
BIO
I
Branch control. When BIO is active, a conditional branch can be executed. When it is low, the processor executes a
conditional branch. The XC instruction samples BIO condition in the pipeline decode phase. Other instructions sample
BIO in the read phase.
XF
O/Z
External flag output (latch signal that can be changed by software). It is set to high by SSBX XF instruction, and set to
low by loading an RSBX XF instruction or ST1. This signal is used as a communication or general output signal when
several DSPs are used. It becomes high impedance when OFF signal is at low level, and is set to high level on reset.
Memory control signal
DS
O/Z
Data, program, or I/O space select signal. It is always at high level, except when it is driven at low level to access a
PS
specific external memory space. It is active while the address is effective. In hold mode, it becomes high impedance
IS
when the OFF signal is at low level.
MSTRB
O/Z
Memory strobe signal. It is always at high level, except when accessing data or program memory through an external
bus. In hold mode, it becomes high impedance when the OFF signal is at low level.
READY
I
Data ready signal. It indicates that an external device has finished preparing accessing a bus.
If it is not ready (READY is at low level), it waits one cycle and checks the READY signal again. At least two software
wait states must be programmed for the processor to detect a READY signal. The READY signal is not sampled until
software wait states are complete.
R/W
O/Z
Read/write signal. It indicates the direction of data transfer with an external device. It is normally at high level (read
mode) except when it goes low to execute a write operation. In hold mode, it becomes high impedance when the
OFF signal is at low level.
SEMICONDUCTOR DATA
Summary of Contents for TS-2000
Page 132: ...TS 2000 X TS 2000 X 134 WIRING ...
Page 142: ...1 2 B A D F C E G I H J 3 5 7 9 4 6 8 10 12 14 11 13 TS 2000 X CIRCUIT DIAGRAM 165 ...
Page 144: ...1 2 B A D F C E G I H J 3 5 7 9 4 6 8 10 12 14 11 13 TS 2000 X CIRCUIT DIAGRAM 169 ...
Page 167: ...234 TS 2000 X MC 52DM MULTI FUNCTION MICROPHONE WITH DTMF Schamatic Diagram ...
