Kenwood TS-2000, Service Manual

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TS-2000/X
Pin name Type* Description
IOSTRB O/Z I/O strobe signal. It is always at high level (read mode) except when accessing an I/O device through an external bus.
In hold mode, it becomes high impedance when the OFF signal is at low level.
HOLD I Hold input signal. Address, data, or control signal control input signal. When this signal is accepted, the address,
data, or control signal becomes high impedance.
HOLDA O/Z Hold response signal. It notifies the external circuits that the processor is in hold state and the address, data and
control signals are high impedance so that they can be used by the external circuits. It becomes high impedance
when the OFF signal is at low level.
MSC O/Z Microstate completion signal. MSC indicates that all software wait states are complete. When several software wait
states are enabled, MSC becomes active at the beginning of the first software wait state and becomes inactive high
at the beginning of the last software wait state. When READY input is connected, MSC inserts an external wait state
forcibly after completion of the last internal wait state. It becomes high impedance when the OFF signal is at low level.
IAQ O/Z Instruction capture signal. It becomes active low when an instruction address is on the address bus. It becomes high
impedance when the OFF signal is at low level.
Oscillator/timer signal
CLKOUT O/Z Master/clock output signal. A signal with the same frequency as the CPU machine cycle is output. The internal machine
cycle is delimited at a rising edge of this signal. It becomes high impedance when the OFF signal is at low level.
CLKMD1 I Clock mode select signal. These input signals are used to select a mode that is initialized after the clock generator is
~ reset. The CLKMD1 to CLKMD3 logic level is latched when the reset pin is low and the clock mode register is
CLKMD3 initialized in the selected mode. The clock mode is changed by software after reset, but the clock mode select signal
is not affected until the device is reset again.
X2/CLKIN I Oscillator input. This is an input to the onchip oscillator. If an internal oscillator is not used, X2/CLKIN functions as a
clock input and is driven by the external clock source.
X1 O Output pin from crystal internal oscillator. If the internal oscillator is not used, do not connect this pin. It does not
become high impedance when the OFF signal is at low level.
TOUT0 O/Z Timer 0 output. When onchip timer 0 count exceeds 0, a pulse is output. It has the same pulse width as CLKOUT.
It becomes high impedance when the OFF signal is at low level.
TOUT1 O/Z Timer 1 output. When onchip timer 1 count exceeds 0, a pulse is output. It has the same pulse width as CLKOUT.
TOUT1 is output from the HPI HINT pin. It is disabled when HPI is disabled. It does not become high impedance
when the OFF signal is at low level.
Multi-channel buffered serial port signal
BCLKR0 I/O/Z Receive clock input. BCLKR can be used as input and output, and becomes input after reset. It is a serial shift clock
BCLKR1 of the receive side buffered serial port.
BDR0 I Serial data reception input.
BDR1
BFSR0 I/O/Z Reception input frame synchronous pulse. BFSR can be used as input and output, and becomes input after reset.
BFSR1 The BFSR pulse ends BDR and initializes data reception.
BCLKX0 I/O/Z Transmission clock. BCLKX is a McBSP transmission serial shift clock. BCLKX can be used as input and output, and
BCLKX1 becomes input after reset. It becomes high impedance when the OFF signal is at low level.
BDX0 O/Z Serial data transmission output. BDX becomes high impedance when transmission is not performed, RS is low, or
BDX1 OFF is low.
BFSX0 I/O/Z Transmission I/O frame synchronizing pulse. The BFSX pulse initializes data transmission. It can be used as input and
BFSX1 output, and becomes input after reset. It becomes high impedance when the OFF signal is low.
Other signals
NC No connection.
SEMICONDUCTOR DATA