Kenwood NEXEDGE NX-800 series Service Manual Download Page 21

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NX-800

CIRCUIT DESCRIPTION

5. PLL Frequency Synthesizer

5-1. VCTCXO (X1)

VCTCXO (X1) generates a reference frequency of

19.2MHz for the PLL frequency synthesizer. This reference
frequency is applied to pin 9 of the PLL IC (IC3) and
connected to IF circuit as a 2nd local signal through Tripler.
The VCTCXO oscillation frequency is determined by DC
voltage of VC terminal. The VC voltage is fixed to 1.65V by R1
and R2, and supplied to VC terminal through IC2. Modulation
signal is also fed to VC terminal through IC2.

The frequency adjustment is achieved by switching the

ratio of dividing frequency that is not adjusted by the DC
voltage impressed to VC. The resolution of adjusting fre-
quency is approximately 4Hz.

5-2. VCO

There is a RX VCO and a TX VCO.
The TX VCO (Q6) generates a transmit carrier and the RX

VCO (Q5) generates a 1st local signal. For the VCO oscillation
frequency, the transmit carrier is 450 to 520 MHz and the 1st
local signal is 391.95 to 461.95MHz.

The VCO oscillation frequency is determined by one sys-

tem of operation switching terminal "T/R" and two systems of
voltage control terminals "C/V" and "V-assist".

The operation switching terminal, "T/R", is controlled by

the control line (/T_R) output from the CPU (IC510). When
the /T_R logic is low, the VCO outputs the transmit carrier
and when it is high, it outputs a 1st local receive signal.

The voltage control terminals, "CV" and "V-assist", are

controlled by the PLL IC (IC3) and CPU (IC510) and the output
frequency changes continuously according to the applied
voltage. For the modulation input terminal, "VCO MOD", the
output frequency changes according to the applied voltage.
This is used to modulate the VCO output. "VCO MOD" works
only when "/T_R" is low.

5-3. PLL IC (IC3)

PLL IC compares the differences in phases of the VCO

oscillation frequency and the VCTCXO reference frequency,
returns the difference to the VCO CV terminal and realizes
the "Phase Locked Loop" for the return control. This allows
the VCO oscillation frequency to accurately match (lock) the
desired frequency.

When the frequency is controlled by the PLL, the

frequency convergence time increases as the frequency
difference increases when the set frequency is changed. To
supplement this, the CPU is used before control by the PLL
IC to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approx. 3.0V.

The desired frequency is set for the PLL IC by the CPU

(IC510) through the 3-line "SDO1", "SCK1", "PCS_RF" serial
bus. Whether the PLL IC is locked or not is monitored by the
CPU through the “PLD” signal line. If the VCO is not the
desired frequency (unlock), the "PLD" logic is low.

5-4. Local Switch (D101, D205)

The connection destination of the signal output from the

buffer amplifier (Q10) is changed with the diode switch
(D101) that is controlled by the transmission power supply,
80T, and the diode switch (D205) that is controlled by the
receive power supply, 50R. If the 80T logic is high, it is con-
nected to a send-side pre-drive (Q101). If the 80T logic is
low, it is connected to a local amplifier (Q208).

Loop
Filter

BUFF

AMP

BUFF

AMP

Ripple

Filter

VCO

150C

TCXO

PLL

IC3