B-2
I/O Address Mapping
KPCI-3160 User’s Manual
NOTE
A typical user of the KPCI-3160 board does not need to read this appen-
dix (except perhaps for the supplementary interrupt illustration under
“
Interrupt example scenario
”). Register level programming of the
KPCI-3160 board is neither practical nor necessary for most users.
Register level interfacing with the PCI bus is more complex than with
the ISA bus. PCI board addresses are mapped automatically in I/O
space or memory, whereas ISA board addresses are assigned manually
by the user in I/O space.
However, under Windows 95/98 only, you may be able to reuse an exist-
ing port I/O application program—if it was designed to work with the
industry-standard 8255 and 82C55 chips—by substituting the automati-
cally-mapped address for the user-assigned address. Refer to “
Using
existing port I/O software to manipulate control and data registers
” at
the end of
Appendix B
.
The DriverLINX driver shipped with your board provides a user-friendly Application Program-
ming Interface (API) that supports Visual C++, Visual Basic, and Delphi programming lan-
guages under Windows 95/98 and Windows NT 4.0. You are encouraged to use the capabilities
of DriverLINX and ignore the rest of the information in this chapter (except perhaps the subsec-
tion “
Interrupt example scenario
,” which may help you to understand how external interrupts
work).
However, there are circumstances in which advanced users may desire or need to bypass Driver-
LINX entirely and write their own drivers. Alternatively, advanced users may wish to program
the KPCI-3160 at the register level using an ActiveX hosting language. Finally, some users may
wish to reuse an existing application program that makes port I/O calls to an ISA-bus digital I/O
board.
Appendix B
discusses the following:
•
General PCI address assignments
•
Control and data register address assignments inside the I/O space, as follows:
–
Assignments for a control and data register map that emulates the assignments of the
8255 and 82C55 chips
–
Assignments for five bits of a special interrupt control/status register, including an exam-
ple scenario showing how the bits are used
•
Some general requirements for manipulating control and data registers
•
Reuse of an existing port I/O application program with the KPCI-3160 board
General PCI address assignments
The PCI specification allows each PCI-bus board to be assigned up to five distinct address
regions for general use at the discretion of the hardware designer. The first region, at base
address BADDR0, is mandatory per the PCI specification, as published by the PCI Special
Interest Group (PCISIG). The other four address regions, located at base addresses BADDR1,
BADDR2, BADDR3, and BADDR4, are optional. The PCI BIOS or the Plug and Play operating
system automatically allocates BADDR0 through BADDR4 at power-up, based on the PCI
boards that it finds installed at that time. After power-up, computer software can read PCI
configuration space to determine the location of BADDR0 through BADDR4. (The term
“computer software” hereafter in
Appendix B
refers to the combination of the application
programming interface (API)/driver—normally, DriverLINX—and the application program. For
information about application programming through DriverLINX, refer to your DriverLINX
documentation.)
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