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KPCI-3160 User’s Manual
I/O Address Mapping
B-7
b. When the first rising or falling edge is missed, the problem is recorded as follows:
1. Board firmware detects the missed interrupt, causing interrupt-missed bit 23 of the
interrupt control/status register to be set to logic high.
2. Computer software, if appropriately programmed, detects that bit 23 has been set and
notifies the user of the missed interrupt.
c. If additional rising or falling edges are missed (edges 2, 3, ...., n), the problems are not
recorded, as follows:
1. No additional interrupt-missed bits are set (there is only one interrupt-missed bit).
2. Computer software cannot further notify the user.
14. The ISR, if appropriately programmed, writes ones (Acknowledge) to clear the interrupt-
pending bit 17 and interrupt-missed bit 23 in the interrupt control/status register to logic low,
which clears interrupt-pending status and interrupt-missing status in board firmware.
15. The ISR, if appropriately programmed, clears the rising/falling edge of bit 6 in the interrupt
control/status register to logic low.
16. The ISR finishes.
17. The ISR dispatcher of the operating system detects that the ISR has finished and sends an
end-of-interrupt instruction to the CPU.
NOTE
The end-of-ISR behavior depends on the operating system being used.
18. The CPU returns to the task that it was executing at the time of the interrupt.
19. At some point, the user circuit may disable interrupts and latching by setting INT_ENN to
logic high.
20. Board firmware detects that INT_ENN is high and rejects interrupt signals at INT_REQ.
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