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List of Illustrations
iii
3
Installation
Figure 3-1
Pin assignments for the KPCI-3160 I/O connector (P101) ........................................................................
3-8
Figure 3-2
Connector locations on the KPIC-3160 board ...........................................................................................
3-9
Figure 3-3
The CONN-3160-D1 accessory ...............................................................................................................
3-10
Figure 3-4
Using additional accessories with the KPCI-3160 ...................................................................................
3-16
Figure 3-5
Contact-closure monitoring at a KPCI-3160 board input ........................................................................
3-17
Figure 3-6
De-bounce circuit for an input of a KPCI-3160 board .............................................................................
3-17
5
Troubleshooting
Figure 5-1
Problem isolation flowchart .......................................................................................................................
5-4
Figure 5-2
Mating connector wiring for loop-back test .............................................................................................
5-14
Figure 5-3
An AIO Panel example ............................................................................................................................
5-16
Figure 5-4
DIO channel tab example .........................................................................................................................
5-17
Figure 5-5
Configuring the digital I/O channels as inputs and outputs .....................................................................
5-19
Figure 5-6
Configuring channel 0 for output bit pattern A ........................................................................................
5-19
Figure 5-7
Proper response of channel 1 input bits when channel o output bits
are set to bit pattern A .......................................................................................................................
5-19
Figure 5-8
Proper response of channel 2 input bits when channel 0 output bits
are set to bit pattern A .......................................................................................................................
5-20
Figure 5-9
Configuring channel 0 for output bit pattern B ........................................................................................
5-20
Figure 5-10
Proper response of channel 1 bits when channel 0 output bits
are set to bit pattern B ........................................................................................................................
5-20
Figure 5-11
Proper response of channel 2 bits when channel 0 output bits
are set to bit pattern B ........................................................................................................................
5-21
Figure 5-12
An AIO Panel example ............................................................................................................................
5-23
Figure 5-13
Configuring the digital I/O channels as inputs and outputs .....................................................................
5-24
Figure 5-14
Configuring channel 0 for output bit pattern A ........................................................................................
5-24
Figure 5-15
Configuring channel 1 for output bit pattern B ........................................................................................
5-25
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