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2-2
Functional Description
Interr
upt and
DMA Control
Control and
Status
Registers
QRAM
Address
Control
256 x 11
Chan.-Gain
QRAM
8 or 16
Channel
Input MUX
Diff
./S
.E.
Select
Gain
Select
Inst.
Amp
.
Unipolar/Bipolar
Select
DC/DC
Con
v
er
ter
1K x 16
FIFO
T
rigger/Gate and
Burst Mode Control
16-Bit
Counter 0
16-Bit
Counter 1
16-Bit
Counter 2
Address
Decode &
Prescaler
Xtal Osc.
Buff
er
Latch
Chan.
0/0
Chan.
7/15
GEXT
MUX [7:4]
82C54
Timer/Counter
TGOUT
SSHO
XPCLK
TGIN
DI [3:0]
DO [3:0]
+15V
-15V
+5V
ISA A
T Bus (16-bit)
Local Control Bus
Note:
The sampling ADC is 12-bit f
or D
AS-1800ST Ser
ies
boards and 16-bit f
or D
AS-1802HR boards.
Figure 2-1.
Bloc
k Dia
gram of Basic D
AS-1800ST/HR Series Boar
ds
Analog
Inputs
8 Diff
.
or
16 S
.E.
DOSTB
Sampling
ADC
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