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A-3
Interrupt levels
3, 5, 7, 10, 11, and 15
Minimum external pacer
clock pulse width
10ns
Maximum external pacer
clock rate
333kHz
Minimum hardware trigger
pulse width
10ns
1
Monotonicity is guaranteed over the operating range.
2
The figures in the table show the electrical noise introduced by the analog front end
but do not include
the uncertainty inherent in the quantization process
. The inherent quantization noise introduced by any
ADC is due to uncertainty at code boundaries and adds a peak-to-peak value of 1 LSB to the electrical
noise; it also makes the rms level 0.5 LSBs.
Table A-2. Analog Input Specifications for DAS-1800HR Series
Feature
DAS-1802HR/HR-DA
Number of channels
Software-selectable as 8 differential or 16 single-ended
Input mode
Software-selectable as unipolar or bipolar
Resolution
16-bits (1 part in 65,536 or 15 ppm)
Data format
16-bit 2’s complement
FIFO size
1024 word
Channel-Gain Control:
Channel QRAM
Gain QRAM
256 X 8 bits (256 channels maximum)
256 X 2 bits (four gain ranges)
Table A-1. Analog Input Specifications for DAS-1800ST Series (cont.)
Feature
DAS-1801ST/ST-DA
DAS-1802ST/ST-DA
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