Troubleshooting
2-12
will be applied to the +RELAY1 line, which energizes relay
K101 to select the 110V setting. Conversely, when the volt-
age at the inverting input is less than 4V, the output of U102
goes high and turns off Q106. With Q106 off, the +8V is re-
moved from K101 and thus, the line voltage setting defaults
to 220V.
The AC power line is tied to C103 through CR102, R113 and
R114 via control line ACL. When the AC power line voltage
is less than approximately 135VAC, sufficient charge re-
mains on C103 to keep the inverting input of U102 above 4V
to ultimately energize K101 (110V setting). When the AC
power line voltage is greater than approximately 18VAC,
charge will be pulled from C103 dropping the voltage at the
inverting input of the comparator to less than 4V. This will
de-energize K101 (220V setting).
HI/LO voltage control circuit
This circuit automatically selects the appropriate HI/LO set-
ting for the available power line voltage. During power-up,
the line voltage is rectified (CR101), divided (R105 and
R107, or R104 and R107) and applied to the base of Q102.
If the voltage level at the base of Q102 is high (above zener
VR101), the transistor will turn on and apply power to the
ISO1+ and ISO1- lines. With power applied to ISO1+ and
ISO1-, U103 will turn on and allow Q105 to be forward bi-
ased. With U103 and Q105 on, TRIG of U106 will be pulled
low and allow its output (OUT) to latch at +8V which will
turn on FET Q104. With Q104 on, the -RELAY2 line will be
connected to common, and thus energize K101 (HI setting).
If the power line voltage decreases to a low level, U103 will
turn off, but the output of U106 will remain latched at +8V.
However, the low line will be driven low turning on U104.
With U104 and Q105 on, +8V will be applied to THR of
U106 forcing its output (OUT) to reset to low. With the gate
of Q104 low, the FET will turn off and open the relay coil cir-
cuit for K101 (LO setting).
The low line is controlled by comparator U628. The invert-
ing input of the comparator is connected to the 2.5V refer-
ence. The non-inverting input monitors (via divider R709
and R711) C611. As previously explained, the typical power
line voltage level will apply around 7.5V to C611. However,
if the line voltage decreases such that the voltage on C611
becomes less than 6V, the voltage level on the non-inverting
input of the comparator will drop below 2.5V causing its out-
put (low line) to go low.
2.10 Built-in test overview
BUILT-IN TEST is used to test and exercise various circuits
and components on the digital board, analog board and A/D
converter board. The Built-in tests are listed in Table 2-7.
Many of the tests are actual pass/fail type tests, while others
are circuit exercises that are used for subsequent tests. Each
Built-in test can be run manually. After a test is manually run,
operation is “frozen” to allow the technician to troubleshoot
the circuit. Detailed troubleshooting documentation for each
Built-in test is provided in paragraph 2.11.
Table 2-7
Built-in test summary
Test
Circuit tested/exercised
100 Series
100.1
101 Series
101.1
102 Series
102.1
103 Series
103.1 - 103.4
103.5
104 Series
104.1
104.2
105 Series
105.1 - 105.6
105.7
105.8
105.11 - 105.18
200 Series
200.1
200.2
201 Series
201.1
201.2
201.3
Memory:
EPROM
Memory:
RAM
Memory:
E
2
PROM
Digital I/O:
Digital Output Bits 1-4
Digital Input
IEEE-488 Bus:
Handshake
Data
Triggers:
System Trigger Bus
External Trigger /Voltmeter Complete
Group Execute Trigger (GET)
Trigger Shorts
A/D Converter:
A/D Communication
A/D Noise
Calibration:
Test Cal Zero
7V Reference
1.75V Reference
