Troubleshooting
2-28
202.2 — Integration period bit I15
Type
Pass/Fail
Fault message
Integration period bit I15
Description
Integration time is set up with I15 and I0 high (longest integration time) and all other I lines low.
The 7 volt reference REFHI generated by U219 and associated circuitry is connected to buffer
U255 to generate REFBUF signal. REFBUF is switched through R263 and U222 pin 5 to U226.
U226 is set up for X1 gain through U227 pin 2 to 3 with /X1 pin 1 low. R274 is the feedback
path of U226. REFLO is switched through R310 and U242 pins 7 to 6, through R311, and to pin
3 of U253. U253 is the buffer for ADGND. ADGND buffer with REFLO signal is connected to
the bottom of the parallel combination of R285 and R286. A/D_IN will be the difference voltage
of REFHI (REFBUF) and REFLO (ADGND). The A/D is triggered and the REFHI reading is
acquired and compared to a calculated value based on the previous reading.
Drawing reference
Analog Board; 2002-100
A/D Converter; 2002-160
Components
Shift registers that set up the I15 through I0 levels, open or shorted lines, or components U816.
Bit patterns
Test 202.3 — Baseline for test 202.4
Type
Circuit Exercise
Fault message
None
Description
Integration time is set up with I14 and I0 high and all other I lines low. This test uses the same
circuit setup as test 202.1. A zero reading is acquired and stored as baseline value for test 202.4.
Drawing reference
Analog Board; 2002-100
A/D Converter; 2002-160
Bit pattern*
Register
—U400—
01111011
—U811—
00001101
—U224—
00010111
—U432—
10000000
—U810—
10000000
—U206—
01110000
—U203—
10001110
—U411—
11111011
—U809—
00000001
—U207—
00110111
—U221—
11101001
—U406—
00000100
AD_STB
MUX_STB
R1_STB
R2_STB
*Bits associated with register IC terminals as follows:
Q
Q
Q
Q
Q
Q
Q
Q
87654321
87654321
87654321
87654321
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4.
