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3�6 ADC Timing Control
3�6�1 Timebase Architecture
ADC
ADC Output
Onboard
200 MHz
Oscillator
200 MHz
X2
Multiplier
PLL
400 MHz
200 MHz
FPGA
For ADC
Data Bus
For ADC
state
machine
Figure 3-11: PXIe-69852 Timebase Architecture
3.6.2 Basic Acquisition Timing
The PXIe-69852 commences acquisition upon receipt of a trigger event originating with software
command, external digital trigger, or the PXI Trigger Bus. The Timebase is a clock provided to the
ADC and acquisition engine for essential timing. The Timebase is from an onboard synthesizer. To
achieve different sampling rates, a scan interval counter is used.
Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer,
the acquisition engine commences acquisition of data from ADC, and stores the sampled data to
the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately
through the DMA engine. The sampled data is generated continuously at the rising edge of Timebase
according to the scan interval counter setting. When sampled data reaches a specified value, in this
example 256, acquisition ends.
