4
1�3�2 Timebas
Sample Clock
Comment
Timebase options
Internal : on board synthesizer
External : CLK IN (front panel),
PXI_CLK10, and PXIe_CLK100
Sampling clock frequency
Internal : 200MHz
3.052kS/s to 200MS/s
External : 40MHz ~ 200MHz
(CLK IN)
Timebase accuracy
< ± 25ppm
External reference clock source Front panel, PXI_CLK10, and
PXIe_CLK100
External reference clock
10MHz
External reference
clock input range
500mVpp ~ 5Vpp
AC / DC compliant, 50Ω load
impedance
External sampling
clock input range
1Vpp ~ 5Vpp
AC / DC compliant, 50Ω load
impedance
Table 1-1: Timebase
1�3�3 Triggers
Trigger Source & Mode
Trigger source
Software, external digital trigger, analog trigger,
PXI_STAR, PXI_trigger bus [0..7], and PXIe_DSTARB
Trigger mode
Post trigger, delay trigger, pre-trigger, or middle trigger, re-trigger for
post trigger and delay trigger modes
Table 1-2: Trigger Source & Mode
Digital Trigger Input
Sources
Front panel SMA connector
Compatibility
3.3 V TTL, 5 V tolerant
Input high threshold
2.0 V
Input low threshold (VIL)
0.8 V
Maximum input overload
-0.5 V ~ +5.5 V
Trigger polarity
Rising or falling edge
Pulse width
20 ns minimum
Table 1-3: Digital Trigger Input
Digital Trigger Output
Compatibility
5 V TTL
Output high threshold (VOH)
2.4 V
Output low threshold (VOL)
0.2 V
Trigger polarity
Positive or negative
