12
3�2�2 Input Range and Data Format
Data format of the PCIe-69814 is 2’s complement. The ADC data of PCIe-69814 is on the
12 MSB of the 16-bit A/D data. D2 to D0 is SDI2 to SDI0, with D3 disregarded. A/D data
structure is as follows.
D15
D14
D13
D12
…�
D3
D2
D1
D0
D15 to D4 bits represent the data from ADC (2’s complement)
D2 is SDI2, D1 SDI1, D0 SDI0, and D3 is disregarded
Table 3-1: Input Range and Data Format
Description
Full scale range
Least significant bit
FSR-1LSB
-FSR
Bipolar Analog
Input
±10V
4.88mV
9.9512V
-10V
±5V
2.44mV
4.99756V
-5V
±1V
0.488mV
0.99512V
-1V
±0.5V
0.244mV
0.499756V
-0.5V
Digital Code
N/A
N/A
7FF0
8000
Comment
SDI bit is assumed to be 0
Table 3-2: Input Range FSR and –FSR Values
Description
Mi1LSB
Midscale
Midscale -1LSB
Bipolar Analog
Input
4.88mV
0V
-4.88mV
2.44mV
0V
-2.44mV
0.488mV
0V
-0.488mV
0.244mV
0V
-0.244mV
Digital Code
0001
0000
FFF0
Comment
SDI bit is assumed to be 0
Table 3-3: Input Range Midscale Values
3�2�3 DMA Data Transfer
The PCIe-69814, a PCIe Gen 1 X 4 device, is equipped with a 200MS/s high sampling rate
ADC, generating a 640 MByte/ second rate.
To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous
data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-
mastering controller releases the burden on the host CPU since data is directly transferred
to the host memory without intervention. Once analog input operation begins, the DMA
returns control of the program. During DMA transfer, the hardware temporarily stores
acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined
DMA buffer in the computer.
