11
3 Operations
This chapter contains information regarding analog input, triggering and timing for the PCIe-
69814.
3.1 Functional Block Diagram
CH0
CH1
CH2
CH3
CLK IN
TRG IN
SDI0
SDI1
SDI2
Analog
Front-End
Calibration
12 Bit ADC
PC
Ie
In
ter
face
FPGA
SSI
Clock
Distribution
Buffer
4
3�2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
Calibration
50
�
/
Hi-Z
High Impe dance
Attenuator
ADC D river
Anti-aliasing
Filter
0
0
0
0
0
12
12-bit ADC
Source
Figure 3-1: Analog Input Architecture
Input Configuration
The input channel terminates with equivalent 50Ω or 1MΩ input impedance (selected by
software). The 12-bit ADC provides not only accurate DC performance but also high signal-
to-noise ratio, and high spurious-free dynamic range in AC performance. The ADC transfers
data to system memory via the high speed PCI Express Gen 1 X 4 interface.
For auto-calibration, internal calibration provides stable and accurate reference voltage to
the AI.
