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3�4 Trigger Sources

In addition to the internal software trigger, the PCI/PXI-69816/26/46 also supports external

analog triggers, external digital triggers, PXI_STAR triggers, PXI Trigger Bus[0..7] and SSI bus..

You can configure the trigger source by software command. Please refer to Figure 3.7 for

trigger architecture.

igge

r Source

Mux

Analog

Trigger

I I

PXI_STAR

PXI Trigger Bus[0:7]

Software Trigger

Analog CH0

Analog CH1

Analog TRG

Circuit

TRG IO

SMB Connector Digital Trigger Input

Trigger

Decision

Trigg

t Mux

TRG IO

SMB Connector

I I

face

SSI_TRIG1

SSI_TRIG2

SSI_START_OP

To Internal

Circuit

Analog CH2

Analog CH3

Digital Trigger Output

I B

(Only available in

PCI version)

Figure 3-7: PCI/PXI-698x6 Trigger Architecture

3�4�1 Software Trigger

Software trigger is generated by software command. The trigger asserts right after executing

specified function calls to begin the operation.

3.4.2 External Digital Trigger

An external digital trigger occurs when a TTL rising edge or a falling edge is detected at the

SMB connector TRG IO on the front panel. As illustrated in Figure 3-8, the trigger polarity

can be selected by software. Note that the signal level of the external digital trigger signal

should be TTL-compatible, and the minimum pulse width is 20 ns.

Rising edge

trigger event

Falling edge

trigger event

Pulse Width > 20 ns

Figure 3-8: External Digital Trigger Polarity and Pulse Width Requirement.

Summary of Contents for PCI-69816H

Page 1: ...PCI PXI 69816 26 46 4 CH 16 Bit 10 20 40 MS s Digitizer with 512 MB SDRAM User s Manual Manual Rev 1 00 Revision Date Jul 16 2016...

Page 2: ...03 China Tel 86 21 5047 5899 Fax 86 21 5047 5899 Email service jytek com Additional information aids and tips that help users perform tasks Information to prevent minor physical injury component damag...

Page 3: ...ling Rate and TIMEBASE Control 23 3 3 1 Internal Oscillator 23 3 3 2 External Clock Through Front Panel 23 3 3 3 External Clock from PXI Interfaces 24 3 3 4 Sampling Rate Control 24 3 3 5 Timebase Exp...

Page 4: ...4 Comparing the Different Trigger Sources from SSI 37 3 8 Physical Location of the PXI and PCI Digitizer 38 3 8 1 Identify PXI Digitizer s Physical Location by Geographic Address 38 3 8 2 Assign a Bo...

Page 5: ...69846 9 Table 1 8 Timebase 11 Table 1 9 Triggering 12 Table 1 10 Data Storage and Transfer 12 Table 1 11 Onboard Reference 12 Table 1 12 General Information 13 Table 2 1 Connector Pin Assignments 16...

Page 6: ...ource and Architecture 23 Figure 3 6 Configuring Different Sampling Rate of a Digitizer 24 Figure 3 7 PCI PXI 698x6 Trigger Architecture 25 Figure 3 8 External Digital Trigger Polarity and Pulse Width...

Page 7: ...ansferred to the host memory The data transfer is performed using scatter gather DMA which provides a high data throughput rate and uses system memory more effectively Flexible Triggering The PCI PXI...

Page 8: ...PXI version Standard height half length PCI form factor PCI version Support 5 V and 3 3 V PCI signaling Support 32 bit 66 MHz PCI interface 4 channels simultaneous single ended analog input 16 bit hi...

Page 9: ...t 1 in 65536 Crosstalk 80 dB at 1MHz for all input ranges at 50 input impedance Table 1 1 Analog Input Specifications Offset Error Model Name PXI 69816D PXI 69826D PXI 69846D PXI 69846W PCI 69846D PXI...

Page 10: ...1 M impedance 0 2 V 1 V 5 1 MHz 9 6 MHz 20 MHz 80 MHz 1 V 50 MHz 0 2 V Input Range PCI 69816H PCI 69826H PXI 69846H PCI 69846H 50 and impedance 1 V 5 V 5 1 MHz 9 6 MHz 20 MHz 1 M impedance 1 V 5 V 90...

Page 11: ...mpedance Input Range PXI 69816D PXI 69826D PXI 69846D PXI 69846W PCI 69846D 0 2 V 5 0 LSBRMS 6 0 LSBRMS 8 0 LSBRMS 15 0 LSBRMS 8 0 LSBRMS 1 V 3 0 LSBRMS 4 0 LSBRMS 5 0 LSBRMS 7 0 LSBRMS 5 0 LSBRMS Inp...

Page 12: ...Range SFDR typical 90 37 dBc 98 65 dBc Effective Number of Bit ENOB typical 12 85 Bit 12 32 Bit Test Conditions Input signal frequency is 0 998 MHz Digitizer sampling rate at 10 MHz with 50 input imp...

Page 13: ...typical 88 29 dBc 93 52 dBc Spurious Free Dynamic Range SFDR typical 88 88dBc 95 52 dBc Effective Number of Bit ENOB typical 12 77 Bit 12 07 Bit Test Conditions Input signal frequency is 0 998 MHz Di...

Page 14: ...ge PXI 69826 1V S Rate 20MS s Input Signal 0 998 MHz 1 0796 dBF 0 1 2 3 4 5 6 7 8 9 10 x 10 6 120 100 80 60 40 20 0 Frequency Hz Magnitude dB PXI 9826 1V S Rate 20MS s Input Signal 0 998 MHz 1 0796 dB...

Page 15: ...ns Input signal frequency is 0 998 MHz Digitizer sampling rate at 40 MHz with 50 input impedance Calculated with 64 K point data Note that these dynamic parameters may vary from one unit to another wi...

Page 16: ...put Signal 0 998 MHz 1 1732 dBFs 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 x 10 7 120 100 80 60 40 20 0 Frequency Hz Magnitude dB PXI 9846 1V S Rate 40MS s Input Signal 0 998 MHz 1 1732 dBFs Figure 1 9 PX...

Page 17: ...846 Timebase Frequency Range 10 MHz 1 MHz 20 MHz 1 MHz 40 MHz 1 MHz Sampling Rate Range 24 bitdividedcounter 10 MS s 0 596 S s 20 MS s 1 192 S s 40 MS s 2 384 S s Internal Oscillator Stability 25 ppm...

Page 18: ...put port Connector Type SMB Compatibility 3 3 V TTL Output Level High threshold VOH 2 4V minimum Low threshold VOL 0 2 maximum Driving Capability 8 mA Minimum Output Pulse Width 20 ns Analog Trigger S...

Page 19: ...uding connectors PXI version Single 3U PXI module 100 mm by 160 mm PCI version Standard height half length PCI card 167 64 mm by 106 68 mm PCI Slot Width 1 slot PCI Bus Interface PCI Signaling Support...

Page 20: ...amaged by static electricity The equipment should be handled on a grounded anti static mat and the operator should wear an anti static wristband during the unpacking and installation procedure Please...

Page 21: ...Mechanical Drawing Figure 2 2 PCI 698x6 Mechanical Drawing The JYTEK PXI 69816 PXI 69826 PXI 69846 is packaged in a Eurocard form factor with PXI specificationsmeasuring160mminlengthand100mminheight...

Page 22: ...nction CLK IN Input SMB The CLK IN is a 50 AC coupled external timebase input TRG IO Input Output SMB The TRG IO is a bidirectional port for external digital trigger input or output CH0 Input BNC Thes...

Page 23: ...or latch 6 Tighten the screw on the front panel 7 Power on the PXI system chassis To remove the module reverse step 2 through 6 above To install the PCI 69816 PCI 69826 PCI 69846 module 1 Turn off you...

Page 24: ...provides drivers for other application environment 2 5 1 WD DASK Legacy Drivers and Support WD DASK is composed for advanced 32 bit kernel drivers for customized DAQ application development WD DASK en...

Page 25: ...cribed in this chapter including the control and setting of signal sources trigger sources trigger modes data transfers and synchronizing multiple modules 3 1 Functional Block Diagram Figure 3 1 PCI 6...

Page 26: ...Figure 3 3 Analog Input Signal Block Diagram 3 2 2 Basic Acquisition Timing The trigger is a signal that starts or stops the acquisition In post trigger mode and delay trigger mode the trigger is use...

Page 27: ...t of a delay count is the period of the TIMEBASE For PCI PXI 69816 the unit is 100ns and for PCI PXI 69846 the unit is 25ns Refer to section 3 5 4 for more detail Re Trg Cnt 24 bit 1 16777215 Re Trigg...

Page 28: ...he following table illustrates the idea transfer characteristics of various input ranges of the PCI PXI 69816 26 46 The data format of the PCI PXI 69816 26 46 is straight binary Description Analog Inp...

Page 29: ...z 20 MHz and 40 MHz for PCI PXI 69816 PCI PXI 69826 and PCI PXI 69846 respectively 3 3 2 External Clock Through Front Panel When you need a specific timebase in some applications that the onboard osci...

Page 30: ...R as timebase clock source Note that the function is only available when the PCI PXI 698x6 is in a PXI system It s not supported when the PCI PXI 69816 26 46 is in a Compact PCI system 3 3 4 Sampling...

Page 31: ...Analog CH2 Analog CH3 Digital Trigger Output SSI Bus Only available in PCI version Figure 3 7 PCI PXI 698x6 Trigger Architecture 3 4 1 Software Trigger Software trigger is generated by software comman...

Page 32: ...Analog Triggers The trigger conditions for analog triggers are illustrated in Figure 3 9 and described as follows Positive slope trigger The trigger event occurs when the trigger signal analog input...

Page 33: ...d as a master module and can output SSI_TRG1 SSI_TRG2 or SSI_START_OP to PXI Trigger Bus Each signal can be routed from one of the PXI Trigger Bus 0 7 by software programming For more detail about the...

Page 34: ...ion 3 5 2 Pre trigger Acquisition Use pre trigger acquisition to collect data before the trigger event The acquisition starts once specified function calls are executed to begin the pre trigger operat...

Page 35: ...ration 3 5 3 Middle trigger Acquisition Use middle trigger acquisition when you want to collect data before and after the trigger event The amount of stored data before and after trigger event can be...

Page 36: ...tion to collect data after several trigger events as illustrated in Figure 3 16 You can program the number of triggers then the digitizer will acquire a specific sample data each time a trigger is acc...

Page 37: ...ce all the data has been stored in the on board memory the data will be transferred to the host computer s memory through bus mastering DMA In a multi user or multi tasking OS like Microsoft Windows L...

Page 38: ...The bi directional SSI I Os provide a flexible connection between modules which allows one SSI master PCI PXI 69816 26 46 to output the SSI signals to other slaves modules to receive the signals Table...

Page 39: ...9816 26 46 is capable of achieving multiple module synchronization Users can use ACLSSI 2 ACL SSI 3 ACL SSI 4 cables to synchronize 2 3 or 4 modules Please refer to Figure 3 20 for the installation of...

Page 40: ...I Signal Locations and Pin Definition 3 7 1 SSI_TIMEBASE As an output the SSI_TIMEBASE signal outputs the onboard LVTTL timebase through PXI trigger bus As an input the PCI PXI 69816 26 46 accepts the...

Page 41: ...l by TIMEBASE as illustrated in Figure 3 22 SSI_TRIG1 Tw Tw 2 TIMEBASE Clocks TIMEBASE SSI_TRIG2 Figure 3 22 SSI_TRIG2 Output Timing As an input the PCI PXI 69816 26 46 accepts the SSI_TRIG2 signal to...

Page 42: ...art signal in a pre trigger or middle trigger acquisition sequence The signal is configured in the rising edge detection mode Figure 3 24 show the SSI_START_OP signal input and output timing requireme...

Page 43: ...software command so multiple PCI PXI 69816 26 46 modules don t start the data acquisition simultaneously which may result in the fact that the amount of stored samples are different if the trigger ev...

Page 44: ...D to a PCI Digitizer When users plug two or more PCI 69816 26 46 modules in one computer board ID provides an effective mechanism for user to identity the specific module With this method users can ac...

Page 45: ...e 3 26 Enlargement of Board ID setting Only dip switches 1 5 are valid for board ID settings Dip switches 6 9 are unused When a dip switch is switched to ON it represents 1 the opposite direction repr...

Page 46: ...1 1 0 1 9 0 1 1 0 1 10 1 0 1 0 1 11 0 0 1 0 1 12 1 1 0 0 1 13 0 1 0 0 1 14 1 0 0 0 1 15 0 0 0 0 1 16 1 1 1 1 0 17 0 1 1 1 0 18 1 0 1 1 0 19 0 0 1 1 0 20 1 1 0 1 0 21 0 1 0 1 0 22 1 0 0 1 0 23 0 0 0 1...

Page 47: ...ng over the power cord If the equipment will not bein usefor long periods of time disconnect theequipment from mains to avoid being damaged by transient overvoltage All cautions and warnings on the eq...

Page 48: ...he equipment is not functioning or does not function according to the user s manual The equipment has been dropped and damaged If the equipment has obvious sign of breakage Never open the equipment Fo...

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