RX-DV5RSL
1-30
3.Pin
function
(3/4)
Pin No.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126-131
132
133, 134
135
136-139
140
141-144
145
146
147
148-153
154
155
156
157, 158
159
160
161
162
163-168
169
170
171
172-176
177
178-180
181
182
183
184-187
188
189
190
191
192
193
195
196
197-200
Symbol
VDDDAC
VSSDAC
DAC3
IOM
DAC2
VAA3
DAC1
VSSA
VREF
NC
DAC0
RSET
COMP
VSS
VIOCLK
VSYNC
HSYNC
VDDIO
VIO
VSSIO
VIO
VDD
AD
VDDIO
AD
PWE
AD
VSSIO
AD
VDDIO
AD
PWE
AD
VDD
SCLK
ACK
VSSIO
AD
VDDIO
PWE
VSS
AD
VSSIO
AD
VDDIO
PWE
ALE
LA
VSSIO
RD
LHLDA
LHLD
VDD
PCS0
XIO
VDDIO
XIO
I/O
O
O
O
O
I
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
I/O
I/O
Function
DAC digital power
DAC digital ground
Video DAC3 output
Cascaded DAC differential output used to dump current into external resistor for power
Video DAC2 output
DAC analog power
Video DAC1 output
DAC analog ground
Input voltage reference for output DACs
Unused
Video DAC output
Current setting resistor of output DACs
Compensation capacitor connection
Core and Ring ground
VCLK input/output for video I/O port function
Bi-directional VSYNC signal for devices
Bi-directional HSYNC signal for devices
I/O pad power =3.3V
Bi-directional digital video port data bus
I/O pad ground
Bi-directional digital video port data bus
Core power =1.8V
Multipleced address/data bus
I/O pad power =3.3V
Multipleced address/data bus
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Multipleced address/data bus
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Multipleced address/data bus
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Multipleced address/data bus
Core power =1.8V
Ecternal bus clock used for programmable host bus peripherals
Programmable WAIT-/ACK-/RDY- control
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Core and Ring ground
Multipleced address/data bus
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Address latch enable
Latched address
I/O pad ground
Read
Bus hold acknwledge in slave mode
Bus hold request from extrnal master in slave mode
Core power =1.8V
Peripheral chip select 0
External input/output
I/O pad power =3.3V
External input/output