RX-DV5RSL
1-36
W986432DH-7 (IC505) : 32 Bits SDRAM
1.Pin layout
1
2
3
4
5
6
7
37
38
39
40
41
42
43
86
85
84
83
82
81
80
50
49
48
47
46
45
44
Vcc
DQ0
VccQ
DQ1~DQ2
VssQ
DQ3~DQ4
VccQ
DQ5~DQ6
VssQ
DQ7
NC
Vcc
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A0~A10
DQM2
Vcc
NC
DQ16
VssQ
DQ17~18
VssQ
Pin No.
Function
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
No connection
Power for input buffers and logic circuit inside DRAM. (+3.3V)
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Referred to RAS
Referred to RAS
Command input. When sampled at the rising edge of the clock RAS,
CAS and WE define the operation to be executed.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
No connection
Select bank to activate dining row address latch time,
or bank to read / write during address latch time.
Multiplexed pins for row and column address. Row address: Ao-A10.
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
No connection
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity.
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
-
-
-
-
-
-
-
-
I/O
-
-
I/O
I/O
I/O
I/O
I/O
Symbol
1
2
3
4~5
6
7~8
9
10~11
12
13
14
15
16
17
18
19
20
21
22~23
24~27
28
29
30
31
32
33~34
35
2.Pin function
